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ORCIDTomoharu Tanaka
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2010 – 2019
- 2016
[c4]Toru Tanzawa
, T. Murakoshi, T. Kamijo, Tomoharu Tanaka, J. J. McNeil, K. Duesman:
Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors. A-SSCC 2016: 165-168- [c3]Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo:
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. ISSCC 2016: 142-144 - 2010
- [c2]Toru Tanzawa, Tomoharu Tanaka, Satoru Tamada, Jiro Kishimoto, Sjigekazu Yamada, Koichi Kawai, Takaaki Ichikawa, P. Chiang, Frank Roohparvar:
A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories. ESSCIRC 2010: 106-109
2000 – 2009
- 2009
- [c1]Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama:
A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS. ISSCC 2009: 236-237 - 2002
- [j10]Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura:
Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid State Circuits 37(1): 84-89 (2002) - 2001
- [j9]Ken Takeuchi, Tomoharu Tanaka:
A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories. IEEE J. Solid State Circuits 36(5): 744-751 (2001)
1990 – 1999
- 1999
- [j8]Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui:
A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. IEEE J. Solid State Circuits 34(5): 675-684 (1999) - 1998
- [j7]Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa:
A multipage cell architecture for high-speed programming multilevel NAND flash memories. IEEE J. Solid State Circuits 33(8): 1228-1238 (1998) - 1997
- [j6]Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi:
A compact on-chip ECC for low cost flash memories. IEEE J. Solid State Circuits 32(5): 662-669 (1997) - [j5]Toru Tanzawa, Tomoharu Tanaka:
A stable programming pulse generator for single power supply flash memories. IEEE J. Solid State Circuits 32(6): 845-851 (1997) - [j4]Toru Tanzawa, Tomoharu Tanaka:
A dynamic analysis of the Dickson charge pump circuit. IEEE J. Solid State Circuits 32(8): 1231-1240 (1997) - 1996
- [j3]Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura:
A double-level-Vth select gate array architecture for multilevel NAND flash memories. IEEE J. Solid State Circuits 31(4): 602-609 (1996) - 1994
- [j2]Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara:
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. IEEE J. Solid State Circuits 29(11): 1366-1373 (1994)
1980 – 1989
- 1989
- [j1]Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka:
An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. IEEE J. Solid State Circuits 24(5): 1238-1243 (1989)
Coauthor Index
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