"A double-level-Vth select gate array architecture for ..."

Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura (1996)

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DOI: 10.1109/4.499738

access: closed

type: Journal Article

metadata version: 2022-07-26

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Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura:
A double-level-V_th select gate array architecture for multilevel NAND flash memories. IEEE J. Solid State Circuits 31(4): 602-609 (1996)

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