"Fault-tolerant architecture in a cache memory control LSI."

Yasushi Ooi et al. (1992)

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DOI: 10.1109/4.126538

access: closed

type: Journal Article

metadata version: 2025-02-03

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Yasushi Ooi, Masahiko Kashimura, Hidenori Takeuchi, Eiji Kawamura:
Fault-tolerant architecture in a cache memory control LSI. IEEE J. Solid State Circuits 27(4): 507-514 (1992)

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