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ORCIDRalph Mason
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2020 – today
- 2024
[c24]Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang
, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri:
7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS. ISSCC 2024: 128-130- 2020
- [j10]Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Shahaboddin Moazzeni, Ralph Mason, Raleigh Smith:
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS. IEEE J. Solid State Circuits 55(3): 580-591 (2020) - [j9]Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub:
A sub-harmonic injection locking clock multiplier with FLL PVT calibrator. Microelectron. J. 98: 104729 (2020)
2010 – 2019
- 2019
- [c23]Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub:
A High-Performance Low Complexity All-Digital Fractional Clock Multiplier. A-SSCC 2019: 73-76 - 2018
- [c22]Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub:
A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator. ISCAS 2018: 1-5 - 2015
- [j8]Zhanjun Bai, Xing Zhou, Ralph D. Mason, Gord Allan:
Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 41-45 (2015) - 2014
- [c21]Zhanjun Bai, Xing Zhou, Ralph Mason:
A novel Injection Locked Rotary Traveling Wave Oscillator. ISCAS 2014: 1768-1771 - 2013
- [c20]Tony Forzley, Ralph Mason:
A 14b threshold configurable dynamically latched comparator for SAR ADCs. SBCCI 2013: 1-5 - 2012
- [j7]Ralph D. Mason, Justin Fortier, Christopher A. DeVries:
Complete SOC Transceiver in 0.18 µm CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking. IEEE J. Solid State Circuits 47(8): 1800-1809 (2012) - [c19]Yasser Soliman, Ralph Mason:
Phase calibration techniques for injection-locking LO-path based phase-shifting phased-array architectures. RWS 2012: 415-418 - 2011
- [c18]Ralph Mason, Justin Fortier, Chris DeVries:
Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking. CICC 2011: 1-4
2000 – 2009
- 2008
- [j6]Christopher A. DeVries, Ralph D. Mason:
Subsampling Architecture for Low Power Receivers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(4): 304-308 (2008) - [c17]Reza Yousefi, Ralph Mason:
A 14-mW 2.4-GHz CMOS transceiver for short range wireless sensor applications. ESSCIRC 2008: 150-153 - 2006
- [c16]Igor Miletic, Ralph Mason:
Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs. CCECE 2006: 971-974 - [c15]Igor Miletic, Ralph Mason:
Quantization noise reduction using multiphase PLLs. ISCAS 2006 - 2004
- [c14]Chris DeVries, Ralph Mason:
A 0.18 μm CMOS 900 MHz receiver front-end using RF Q-enhanced filters. ISCAS (4) 2004: 325-328 - [c13]Syed Irfan Ahmed, Ralph D. Mason:
Improving the acquisition time of a PLL-based, integer-N frequency synthesizer. ISCAS (4) 2004: 365-368 - [c12]Ralph Mason, Chris DeVries, Eugene Ivanov:
An RF sub-sampling mixer, PGA and Sigma Delta ADC for conversion at 900 MHz. ISCAS (1) 2004: 477-480 - 2003
- [c11]Hesham Ahmed, Christopher A. DeVries, Ralph Mason:
A digitally tuned 1.1 GHz subharmonic injection-locked VCO in 0.18μm CMOS. ESSCIRC 2003: 81-84 - [c10]H. Ahmed, Chris DeVries, Ralph Mason:
RF, Q-enhanced bandpass filters in standard 0.18µm CMOS with direct digital tuning. ISCAS (1) 2003: 577-580 - [c9]Syed Irfan Ahmed, Ralph D. Mason:
A dual edge-triggered phase-frequency detector architecture. ISCAS (1) 2003: 721-724 - 2002
- [c8]Chris DeVries, Ralph Mason:
A 0.18μm CMOS, high Q-enhanced bandpass filter with direct digital tuning. CICC 2002: 279-282 - 2001
- [c7]Mohsen Moussavi, Ralph Mason, Calvin Plett:
A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD. CICC 2001: 161-164
1990 – 1999
- 1999
- [j5]Narate Lertpalangsunti, Christine W. Chan, Ralph Mason, Paitoon Tontiwachwuthikul:
A toolset for construction of hybrid intelligent forecasting systems: application for water demand prediction. Artif. Intell. Eng. 13(1): 21-42 (1999) - [j4]Ralph Mason, Shing Ma:
Analog DFT Using an Undersampling Technique. IEEE Des. Test Comput. 16(4): 84-88 (1999) - [j3]Ralph Mason, Shing Ma:
Mixed Signal DFT at GHz Frequencies. J. Electron. Test. 15(1-2): 31-39 (1999) - [j2]Anh Dinh, Ralph Mason, Ron Palmer, Ken Runtz:
Phase Measurements for Direct Conversion AM Radio Navigation. J. Intell. Transp. Syst. 5(3): 241-250 (1999) - [c6]Peter M. Nyasulu, Ralph Mason, W. Martin Snelgrove, Duncan G. Elliott:
Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system. CICC 1999: 631-634 - [c5]Shijun Yang, Ralph Mason, Calvin Plett:
6.5 mW CMOS low noise amplifier at 1.9 GHz. ISCAS (2) 1999: 85-88 - [c4]Anh Dinh, Ralph Mason, Joe Toth:
High speed V.32 trellis encoder/decoder implementation using FPGA. ISCAS (4) 1999: 295-298 - [c3]Chang N. Zhang, Ming Y. Deng, Ralph Mason:
A VLSI Programmable Cellular Automata Array for Multiplication in GF (2n). PDPTA 1999: 1118-1123 - 1998
- [c2]Chang N. Zhang, Ming Y. Deng, Ralph Mason:
Two Improved Algorithms and Hardware Implementations for Key Distribution Using Extended Programmable Cellular Automata. ACSAC 1998: 244-249 - [c1]Ralph Mason, Shing Ma:
Mixed Signal DFT at GHz Frequencies. VTS 1998: 245-253 - 1995
- [j1]Ralph D. Mason, William Robertson:
Mapping hierarchical neural networks to VLSI hardware. Neural Networks 8(6): 905-913 (1995)
Coauthor Index
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