"A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for ..."

Dirk Pfaff et al. (2020)

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DOI: 10.1109/JSSC.2019.2946134

access: closed

type: Journal Article

metadata version: 2020-08-30

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Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Shahaboddin Moazzeni, Ralph Mason, Raleigh Smith:
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS. IEEE J. Solid State Circuits 55(3): 580-591 (2020)

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