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ORCIDHeinrich Klar
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2010 – 2019
- 2016
[c12]Adel Fatemi
, Heinrich Klar, Friedel Gerfers:
Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm. ISCAS 2016: 2387-2390
2000 – 2009
- 2005
- [c11]Yi Yin, Heinrich Klar, Peter Wennekers:
A cascade 3-1-1 multibit ΣΔ A/D modulator with reduced sensitivity to non-idealities. ISCAS (4) 2005: 3087-3090 - 2004
- [c10]Yi Yin, Heinrich Klar, Peter Wennekers:
A novel broadband cascade sigma-delta analog-to-digital converter. Circuits, Signals, and Systems 2004: 471-476 - 2003
- [j9]Nasser Mehrtash, Dietmar Jung, Heinrich Klar:
Image preprocessing with dynamic synapses. Neural Comput. Appl. 12(1): 33-41 (2003) - [j8]Nasser Mehrtash, Dietmar Jung, Heik Heinrich Hellmich, Tim Schönauer, Vi Thanh Lu, Heinrich Klar:
Synaptic plasticity in spiking neural networks (SP2INN): a system approach. IEEE Trans. Neural Networks 14(5): 980-992 (2003) - 2002
- [j7]Martin Schäfer, Tim Schönauer, Carsten Wolff, Georg Hartmann, Heinrich Klar, Ulrich Rückert:
Simulation of spiking neural networks -- architectures and implementations. Neurocomputing 48(1-4): 647-679 (2002) - [j6]Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar:
NeuroPipe-Chip: A digital neuro-processor for spiking neural networks. IEEE Trans. Neural Networks 13(1): 205-213 (2002) - 2000
- [c9]Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar:
Simulation of a Digital Neuro-Chip for Spiking Neural Networks. IJCNN (4) 2000: 490-498
1990 – 1999
- 1998
- [j5]Martin Ehlert, Heinrich Klar:
A 12-bit medium-time analog storage device in a CMOS standard process. IEEE J. Solid State Circuits 33(7): 1139-1143 (1998) - 1997
- [c8]Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar:
An Improved Multiplexed Resistive Network for Analog Image Preprocessing. ICANN 1997: 1169-1174 - [c7]Axel Jahnke, Tim Schönauer, Ulrich Roth, K. Mohraz, Heinrich Klar:
Simulation of Spiking Neural Networks on Different Hardware Platforms. ICANN 1997: 1187-1192 - [c6]Ulrich Roth, Axel Jahnke, Heinrich Klar:
On-Line Hebbian Learning for Spiking Neurons: Architecture of the Weight-Unit of NESPINN. ICANN 1997: 1217-1222 - [c5]Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar:
A New Bio-inspired Algorithm for Early Vision Edge Detection and Image Segmentation. IWANN 1997: 1107-1114 - [c4]Ulrich Roth, Marc Walker, Arne Hilmann, Heinrich Klar:
Dynamic Path Planning with Spiking Neural Networks. IWANN 1997: 1355-1363 - 1996
- [j4]Jorg-Michael Green, Heinrich Klar:
A CMOS gate array architecture for digital signal processing applications. IEEE J. Solid State Circuits 31(3): 410-418 (1996) - 1995
- [j3]T. Juhnke, Heinrich Klar:
Calculation of the soft error rate of submicron CMOS logic circuits. IEEE J. Solid State Circuits 30(7): 830-834 (1995) - [j2]O. Salomon, Jorg-Michael Green, Heinrich Klar:
General algorithms for a simplified addition of 2's complement numbers. IEEE J. Solid State Circuits 30(7): 839-844 (1995) - [c3]S. R. Kadivar, Doris Schmitt-Landsiedel, Heinrich Klar:
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. ICCAD 1995: 554-561 - [c2]Ulrich Roth, Axel Jahnke, Heinrich Klar:
Hardware Requirements for Spike-Processing Neural Networks. IWANN 1995: 720-727 - 1993
- [j1]Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar:
Design of a general-purpose neural signal processor. Neurocomputing 5(1): 17-23 (1993) - [c1]O. Salomon, Heinrich Klar:
Self-Timed Fully Pipelined Multipliers. Asynchronous Design Methodologies 1993: 45-55
Coauthor Index
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