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2010 – 2019
- 2011
[c3]Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Dominik Langen, Jörg Berthold, R. Kramer, A. Schackow, Cyprian Grassmann, Mirko Sauermann, P. Szreder, F. Capar, G. Obradovic, W. Xu, Nico Brüls, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington:
Architecture and implementation of a Software-Defined Radio baseband processor. ISCAS 2011: 2193-2196
2000 – 2009
- 2003
- [j5]Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer:
A 100-GOPS Programmable Processor for Vehicle Vision Systems. IEEE Des. Test Comput. 20(1): 8-16 (2003) - [j4]Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer:
100 GOPS vision processor for automotive applications. SIGARCH Comput. Archit. News 31(1): 60-68 (2003)
1990 – 1999
- 1995
- [c2]Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer:
SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. IPPS 1995: 774-781 - 1993
- [j3]Ulrich Ramacher, Wolfgang Raab, Joachim K. Anlauf, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Reinhard Männer, Joachim Gläß, Andreas Wurz:
Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. Int. J. Neural Syst. 4(4): 333-336 (1993) - [j2]Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar:
Design of a general-purpose neural signal processor. Neurocomputing 5(1): 17-23 (1993) - [j1]Ulrich Ramacher, Jörg Beichter, Nico Brüls:
A general-purpose signal processor architecture for neurocomputing and preprocessing applications. J. VLSI Signal Process. 6(1): 45-56 (1993) - [c1]Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder:
Architecture and VLSI Design of a VLSI Neural Signal Processor. ISCAS 1993: 1975-1978
Coauthor Index
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