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ORCIDSIGARCH Computer Architecture News, Volume 31
Volume 31, Number 1, March 2003
- Jack B. Dennis:
Fresh Breeze: a multiprocessor chip architecture guided by modular programming principles. 7-15 - David Morano, Alireza Khalafi, David R. Kaeli, Augustus K. Uht:
Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture. 16-25 - George Almási, Calin Cascaval
, José G. Castaños, Monty Denneau, Derek Lieber, José E. Moreira, Henry S. Warren Jr.:
Dissecting Cyclops: a detailed analysis of a multithreaded architecture. 26-38 - Mohamed M. Zahran:
On cache memory hierarchy for Chip-Multiprocessor. 39-48 - Gary Gréwal, Thomas Charles Wilson, Andrew Morton:
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors. 49-59 - Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer:
100 GOPS vision processor for automotive applications. 60-68 - Nikos Pitsianis, Gerald G. Pechanek:
Indirect VLIW memory allocation for the ManArray multiprocessor DSP. 69-74 - Naohiko Shimizu, Ken Takatori:
A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications. 75-84 - Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Fine-grain design space exploration for a cartographic SoC multiprocessor. 85-92
- Mark Thorson:
Internet nuggets. 93-96
Volume 31, Number 2, May 2003
- Allan Gottlieb, Kai Li:
30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA. IEEE Computer Society 2003, ISBN 0-7695-1945-8 [contents]
Volume 31, Number 3, June 2003
- Anthony S. Fong:
A computer architecture with access control and cache option tags on individual instruction operands. 1-5 - Edwin J. Tan, Wendi Beth Heinzelman:
DSP architectures: past, present and futures. 6-19 - Lucian N. Vintan, Marius Sbera, Ioan Z. Mihu, Adrian Florea:
An alternative to branch prediction: pre-computed branches. 20-29 - Mark A. Heinrich, Mainak Chaudhuri:
Ocean warning: avoid drowning. 30-32 - Jean-Louis Lafitte:
Qualitatively matching computer architecture with Turing machine. 33-41 - Takenori Koushiro, Toshinori Sato, Itsujiro Arita:
A trace-level value predictor for Contrail processors. 42-47
- Mark Thorson:
Internet nuggets. 48-54
Volume 31, Number 4, September 2003
- Mikkel Thorup:
Combinatorial power in multimedia processors. 5-11 - Gary K. W. Hau, Anthony S. Fong, Mok Pak Lun:
Support of Java API for the jHISC system. 12-17 - Mok Pak Lun, Richard Li, Anthony S. Fong:
Method manipulation in an object-oriented processor. 18-25
- Mark Thorson:
Internet nuggets. 26-32
Volume 31, Number 5, December 2003
- Kristopher C. Breen, Duncan G. Elliott:
Aliasing and anti-aliasing in branch history table prediction. 1-4 - Ryan W. S. Yu, Gary K. W. Hau, Anthony S. Fong:
Test bench for software development of object-oriented processor. 5-9 - Mok Pak Lun, Anthony S. Fong, Gary K. W. Hau:
Object-oriented processor requirements with instruction analysis of Java programs. 10-15
- Mark Thorson:
Internet nuggets. 16-21
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