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2020 – today
- 2024
[c30]Vipin Patel, Swarnendu Biswas, Mainak Chaudhuri:
Leveraging Cache Coherence to Detect and Repair False Sharing On-the-fly. MICRO 2024: 823-839- 2021
- [c29]Mainak Chaudhuri:
Zero Directory Eviction Victim: Unbounded Coherence Directory and Core Cache Isolation. HPCA 2021: 277-290 - [c28]Mainak Chaudhuri:
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions. ISCA 2021: 71-84 - 2020
- [j11]Moumita Das, Ansuman Banerjee
, Mainak Chaudhuri, Bhaskar Sardar:
Shared Pattern History Tables in Multicomponent Branch Predictors With a Dealiasing Cache. IEEE Embed. Syst. Lett. 12(3): 95-98 (2020)
2010 – 2019
- 2019
- [c27]Mainak Chaudhuri, Jayesh Gaur, Sreenivas Subramoney:
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth. ICCD 2019: 109-118 - 2017
- [j10]Mainak Chaudhuri, Mukesh Agrawal, Jayesh Gaur, Sreenivas Subramoney:
Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches. ACM Trans. Archit. Code Optim. 14(1): 7:1-7:29 (2017) - [j9]Siddharth Rai, Mainak Chaudhuri:
Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors. ACM Trans. Embed. Comput. Syst. 16(5s): 133:1-133:23 (2017) - [c26]Jayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney:
Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources. HPCA 2017: 13-24 - [c25]Sudhanshu Shukla, Mainak Chaudhuri:
Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking. HPCA 2017: 205-216 - [c24]Sudhanshu Shukla, Mainak Chaudhuri:
Sharing-Aware Efficient Private Caching in Many-Core Server Processors. ICCD 2017: 485-492 - [c23]Siddharth Rai, Mainak Chaudhuri:
Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors. IPDPS Workshops 2017: 18-29 - 2016
- [c22]Siddharth Rai, Mainak Chaudhuri:
Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors. ICS 2016: 3:1-3:14 - [c21]Anirban Ghose, Soumyajit Dey, Pabitra Mitra, Mainak Chaudhuri:
Divergence Aware Automated Partitioning of OpenCL Workloads. ISEC 2016: 131-135 - [c20]Prakhar Banga, Atul Pai, Subhajit Roy, Mainak Chaudhuri:
Accelerating schedule space exploration of multi-threaded programs with GPUs. MEMOCODE 2016: 115-124 - 2015
- [c19]Sudhanshu Shukla, Mainak Chaudhuri:
Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems. ICCD 2015: 557-564 - 2013
- [c18]Ragavendra Natarajan, Mainak Chaudhuri:
Characterizing multi-threaded applications for designing sharing-aware last-level cache replacement policies. IISWC 2013: 1-10 - [c17]Jayesh Gaur, Raghuram Srinivasan, Sreenivas Subramoney, Mainak Chaudhuri:
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads. MICRO 2013: 395-407 - 2012
- [c16]Mainak Chaudhuri, Jayesh Gaur, Nithiyanandan Bashyam, Sreenivas Subramoney, Joseph Nuzman:
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches. PACT 2012: 293-304 - [c15]Prabhakar Misra, Mainak Chaudhuri:
Performance Evaluation of Concurrent Lock-free Data Structures on GPUs. ICPADS 2012: 53-60 - 2011
- [c14]Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney:
Bypass and insertion algorithms for exclusive last-level caches. ISCA 2011: 81-92 - 2010
- [c13]Santhosh Sharma Ananthramu, Deepak Majeti, Sanjeev Kumar Aggarwal, Mainak Chaudhuri:
Improving speculative loop parallelization via selective squash and speculation reuse. PACT 2010: 543-544
2000 – 2009
- 2009
- [j8]B. C. Vishwas, Abhishek Gadia, Mainak Chaudhuri:
Implementing a parallel matrix factorization library on the cell broadband engine. Sci. Program. 17(1-2): 3-29 (2009) - [c12]Mainak Chaudhuri:
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches. HPCA 2009: 227-238 - [c11]Mainak Chaudhuri:
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. MICRO 2009: 401-412 - 2007
- [j7]Mainak Chaudhuri, Mark A. Heinrich:
Integrated Memory Controllers with Parallel Coherence Streams. IEEE Trans. Parallel Distributed Syst. 18(8): 1159-1173 (2007) - [c10]Jugash Chandarlapati, Mainak Chaudhuri:
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation. ICCD 2007: 423-430 - [c9]Lakshmana Rao Vittanala, Mainak Chaudhuri:
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors. ICPP 2007: 4 - [c8]Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark A. Heinrich:
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads. ISPASS 2007: 242-253 - [c7]Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez:
Scavenger: A New Last Level Cache Architecture with Global Block Priority. MICRO 2007: 421-432 - 2006
- [j6]Abhas Kumar, Nisheet Jain, Mainak Chaudhuri:
Long-latency branches: how much do they matter? SIGARCH Comput. Archit. News 34(3): 9-15 (2006) - 2005
- [c6]Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez:
Checkpointed Early Load Retirement. HPCA 2005: 16-27 - 2004
- [j5]Daehyun Kim, Mainak Chaudhuri, Mark A. Heinrich, Evan Speight:
Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems. IEEE Trans. Computers 53(3): 288-307 (2004) - [j4]Mainak Chaudhuri, Mark A. Heinrich:
The Impact of Negative Acknowledgments in Shared Memory Scientific Applications. IEEE Trans. Parallel Distributed Syst. 15(2): 134-150 (2004) - [j3]Mainak Chaudhuri, Mark A. Heinrich:
Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols. IEEE Trans. Parallel Distributed Syst. 15(8): 699-712 (2004) - [c5]Mainak Chaudhuri, Mark A. Heinrich:
SMTp: An Architecture for Next-generation Scalable Multi-threading. ISCA 2004: 124-137 - 2003
- [j2]Mark A. Heinrich, Mainak Chaudhuri:
Ocean warning: avoid drowning. SIGARCH Comput. Archit. News 31(3): 30-32 (2003) - [j1]Mainak Chaudhuri, Mark A. Heinrich, Chris Holt, Jaswinder Pal Singh, Edward Rothberg, John L. Hennessy:
Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation. IEEE Trans. Computers 52(7): 862-880 (2003) - [c4]Daehyun Kim, Mainak Chaudhuri, Mark A. Heinrich:
Active Memory Techniques for ccNUMA Multiprocessors. IPDPS 2003: 10 - 2002
- [c3]Daehyun Kim, Mainak Chaudhuri, Mark A. Heinrich:
Leveraging cache coherence in active memory systems. ICS 2002: 2-13 - [c2]Mark A. Heinrich, Evan Speight, Mainak Chaudhuri:
Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters. ISHPC 2002: 78-92 - [c1]Mainak Chaudhuri, Daehyun Kim, Mark A. Heinrich:
Cache Coherence Protocol Design for Active Memory Systems. PDPTA 2002: 83-89
Coauthor Index
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