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ORCIDThomas Charles Wilson
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2000 – 2009
- 2004
[c14]Gary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji:
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. VLSI Design 2004: 855-862- 2003
- [j5]Gary William Grewal, Thomas Charles Wilson:
Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T). Int. J. Comput. Intell. Appl. 3(1): 45-64 (2003) - [j4]Gary Gréwal, Thomas Charles Wilson, Andrew Morton:
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors. SIGARCH Comput. Archit. News 31(1): 49-59 (2003) - 2002
- [c13]Gary William Grewal, Thomas Charles Wilson, Christopher W. Nell:
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks. AI 2002: 325-333 - 2001
- [j3]Gary William Grewal, Thomas Charles Wilson:
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding. Int. J. Comput. Intell. Appl. 1(1): 91-110 (2001) - [c12]Gary William Grewal, Thomas Charles Wilson:
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). MICRO 2001: 192-202
1990 – 1999
- 1997
- [c11]Gary William Grewal, Thomas Charles Wilson:
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design. VLSI Design 1997: 51-56 - [c10]Thomas Charles Wilson, Gary William Grewal:
Shake And Bake: A Method of Mapping Code to Irregular DSPs. VLSI Design 1997: 506-508 - 1996
- [j2]Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia:
A Modified Approach to Test Plan Generation for Combinational Logic Blocks. VLSI Design 4(3): 243-256 (1996) - [c9]J. Shu, Thomas Charles Wilson, Dilip K. Banerji:
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation. VLSI Design 1996: 73-76 - 1995
- [j1]Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji:
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. VLSI Design 3(1): 21-36 (1995) - 1994
- [c8]Thomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji:
An ILP-based approach to code generation. Code Generation for Embedded Processors 1994: 103-118 - [c7]Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji:
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. ICCD 1994: 581-586 - [c6]Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji:
An integrated approach to retargetable code generation. HLSS 1994: 70-75 - 1993
- [c5]Thomas Charles Wilson, Manoj K. Garg, R. Deadman, Ben Halley, Dilip K. Banerji:
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis. Great Lakes Symposium on VLSI 1993: 132-138 - [c4]Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji:
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design 1993: 192-197 - 1992
- [c3]Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia:
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test. VLSI Design 1992: 354-355 - 1991
- [c2]Thomas Charles Wilson, Anupam Basu, Dilip K. Banerji, Jayanti C. Majithia:
Test plan generation and concurrent scheduling of tests in the presence of conflicts. Great Lakes Symposium on VLSI 1991: 243-248 - [c1]Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia:
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. Great Lakes Symposium on VLSI 1991: 340-341
Coauthor Index
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