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ORCIDYasuhiro Nakakura
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1990 – 1999
- 1998
[j2]Takehiro Kamada, Toshihiko Fukuoka, Yuji Nakai, Yoshihiko Fukumoto, Yasuhiro Nakakura, Katsuhiko Ueda, Tomonori Shiomi, Kazuhiro Ota:
An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting. J. VLSI Signal Process. 18(2): 167-175 (1998)- 1992
- [c3]Hiraku Nakano, Masaitsu Nakajima, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida:
An Accurate, High Speed Implementation of Division by the Quasi-Unity Divisor Method. IFIP Congress (1) 1992: 261-267 - 1991
- [c2]Hiroshi Kadota, Katsuyuki Kaneko, Ichiro Okabayashi, Tadashi Okamoto, T. Mimura, Yasuhiro Nakakura, Akiyoshi Wakatani, Masaitsu Nakajima, Junji Nishikawa, K. Zaiki, Tatsuo Nogi:
Parallel computer ADENART - its architecture and application. ICS 1991: 1-8 - [c1]Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, Hiroshi Kadota:
OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications. ISCA 1991: 160-168
1980 – 1989
- 1989
- [j1]Katsuyuki Kaneko, Tadashi Okamoto, Masaitsu Nakajima, Yasuhiro Nakakura, Satoshi Gokita, Junji Nishikawa, Yuji Tanikawa, Hiroshi Kadota:
A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit. IEEE J. Solid State Circuits 24(5): 1331-1340 (1989)
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