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William J. Bowhill
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2020 – today
- 2022
- [c6]Nevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda:
Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor. ISSCC 2022: 44-46
2010 – 2019
- 2016
- [j7]William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Oscar Mendoza, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Brian Brock, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker:
The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family. IEEE J. Solid State Circuits 51(1): 92-104 (2016) - 2015
- [c5]Ankush Varma, William J. Bowhill, Jason Crop, Corey Gough, Brian Griffith, Dan Kingsley, Krishna Sistla:
Power management in the Intel Xeon E5 v3. ISLPED 2015: 371-376 - [c4]William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker:
4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family. ISSCC 2015: 1-3 - [c3]Sanquan Song, Jian Xu, Fengxiang Cai, Xin Ma, Zibing Yang, Matthew Becker, Larry Tate, Byungsub Kim, Samuel Palermo, William J. Bowhill:
An input pole tuned switching equalization scheme for high-speed serial links. MWSCAS 2015: 1-4 - 2012
- [j6]Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw:
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. IEEE J. Solid State Circuits 47(1): 177-193 (2012) - 2011
- [c2]Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski:
A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. ISSCC 2011: 84-86
1990 – 1999
- 1998
- [j5]Paul E. Gronowski, William J. Bowhill, Ronald P. Preston, Michael K. Gowan, Randy L. Allmon:
High-performance microprocessor design. IEEE J. Solid State Circuits 33(5): 676-686 (1998) - [c1]Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill:
A highly testable and diagnosable fabrication process test chip. ITC 1998: 853-861 - 1996
- [j4]Paul E. Gronowski, William J. Bowhill, Dale R. Donchin, Randel P. Blake-Campos, David A. Carlson, Edward R. Equi, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Andy Olesin, Date J. W. Noorlag, Ronald P. Preston:
A 433-MHz 64-b quad-issue RISC microprocessor. IEEE J. Solid State Circuits 31(11): 1687-1696 (1996) - 1995
- [j3]William J. Bowhill, Shane L. Bell, Bradley J. Benschneider, Andrew J. Black, Sharon M. Britton, Ruben W. Castelino, Dale R. Donchin, John H. Edmondson, Harry R. Fair III, Paul E. Gronowski, Anil K. Jain, Patricia L. Kroesen, Marc E. Lamere, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Ronald P. Preston, Sribalan Santhanam, Timothy A. Shedd, Michael J. Smith, Stephen C. Thierauf:
Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU. Digit. Tech. J. 7(1) (1995) - [j2]Bradley J. Benschneider, Andrew J. Black, William J. Bowhill, Sharon M. Britton, Daniel E. Dever, Dale R. Donchin, Robert J. Dupcak, Richard M. Fromm, Mary K. Gowan, Paul E. Gronowski, Michael Kantrowitz, Marc E. Lamere, Shekhar Mehta, Jeanne E. Meyer, Robert O. Mueller, Andy Olesin, Ronald P. Preston, Donald A. Priore, Sribalan Santhanam, Michael J. Smith, Gilbert M. Wolrich:
A 300-MHz 64-b quad-issue CMOS RISC microprocessor. IEEE J. Solid State Circuits 30(11): 1203-1214 (1995)
1980 – 1989
- 1989
- [j1]Bradley J. Benschneider, William J. Bowhill, Elizabeth M. Copper, Moshe Gavrielov, Paul E. Gronowski, Vijay K. Maheshwari, Victor Peng, Jeffrey D. Pickholtz, Sridhar Samudrala:
A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor. IEEE J. Solid State Circuits 24(5): 1317-1323 (1989)
Coauthor Index
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