"On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM."

Stanley E. Schuster et al. (1992)

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DOI: 10.1109/4.142604

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type: Journal Article

metadata version: 2025-02-03

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Stanley E. Schuster, Terry I. Chappell, Barbara A. Chappell, Robert L. Franch:
On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM. IEEE J. Solid State Circuits 27(7): 1073-1079 (1992)

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