"A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with ..."

Hitoshi Okamura et al. (1995)

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DOI: 10.1109/4.475707

access: closed

type: Journal Article

metadata version: 2023-05-03

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Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki:
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. IEEE J. Solid State Circuits 30(11): 1196-1202 (1995)

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