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ORCIDPanagiotis Merakos
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2010 – 2019
- 2010
[c8]Michalis K. Tsiampas, Dimitrios Bountas, Panagiotis Merakos, Nestoras E. Evmorfopoulos, Sotiris Bantas, George I. Stamoulis:
A power grid analysis and verification tool based on a Statistical Prediction Engine. ICECS 2010: 839-842
2000 – 2009
- 2004
- [j11]Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis:
A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-μm CMOS transceiver for 802.11a/b/g wireless LAN. IEEE J. Solid State Circuits 39(7): 1180-1184 (2004) - [c7]Nikos Haralabidis, Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis:
A cost-efficient 0.18 μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications. CICC 2004: 405-408 - 2003
- [j10]Iason Vassiliou, Kostis Vavelidis, Theodore Georgantas, Sofoklis Plevridis, Nikos Haralabidis, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Yiannis Kokolakis, Panagiotis Merakos, Jacques C. Rudell, Akira Yamanaka, Stamatis Bouras, Ilias Bouras:
A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN. IEEE J. Solid State Circuits 38(12): 2221-2231 (2003) - [j9]Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis
, Constantinos E. Goutis:
Power efficient data path synthesis of sum-of-products computations. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 446-450 (2003) - [c6]Kostis Vavelidis, Iason Vassiliou, Theodore Georgantas, Akira Yamanaka, Spyros Kavadias, George Kamoulakos, Charalampos Kapnistis, Yiannis Kokolakis, Aris Kyranas, Panagiotis Merakos, Ilias Bouras, Stamatis Bouras, Sofoklis Plevridis, Nikos Haralabidis:
A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18μm CMOS RF transceiver for 802.11a/b/g wireless LAN. ESSCIRC 2003: 221-224 - 2002
- [j8]Konstantinos Masselos, Spyros Theoharis, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis:
Memory accesses reordering for interconnect power reduction in sum-of-products computations. IEEE Trans. Signal Process. 50(11): 2889-2899 (2002) - [j7]Panagiotis K. Merakos, Konstantinos Masselos, Constantinos E. Goutis:
Power Efficient Hierarchical Scheduling for DSP Transformations. VLSI Design 14(2): 203-217 (2002) - [c5]Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis:
Power Efficient Vector Quantization Design Using Pixel Truncation. PATMOS 2002: 409-418 - 2000
- [j6]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power architectures for digital signal processing. J. Syst. Archit. 46(7): 551-571 (2000) - [c4]Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power synthesis of sum-of-products computation (poster session). ISLPED 2000: 234-237
1990 – 1999
- 1999
- [j5]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 492-497 (1999) - [j4]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis. VLSI Design 10(2): 177-202 (1999) - [c3]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power synthesis of sum-of-product computation in DSP algorithms. ISCAS (6) 1999: 420-423 - 1998
- [j3]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
A novel algorithm for low-power image and video coding. IEEE Trans. Circuits Syst. Video Technol. 8(3): 258-263 (1998) - [j2]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Trade-Off Analysis of a Low-Power Image Coding Algorithm. J. VLSI Signal Process. 18(1): 65-80 (1998) - [c2]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low-power implementation of discrete wavelet transform. EUSIPCO 1998: 1-4 - 1996
- [c1]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis:
Low-power image decoding using fractals. ICECS 1996: 748-751 - 1994
- [j1]Evaggelinos P. Mariatos, Panagiotis Merakos, Michael K. Birbas, Alexios N. Birbas:
Hardware programming using C++. Microprocess. Microprogramming 40(10-12): 817-820 (1994)
Coauthor Index
aka: Costas E. Goutis
aka: Konstantinos Masselos
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