"A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC."

Eric Siragusa, Ian Galton (2004)

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DOI: 10.1109/JSSC.2004.836230

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type: Journal Article

metadata version: 2022-04-22

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Eric Siragusa, Ian Galton:
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. IEEE J. Solid State Circuits 39(12): 2126-2138 (2004)

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