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ORCIDRajamohana Hegde
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2000 – 2009
- 2004
[j4]Rajamohana Hegde, Naresh R. Shanbhag:
A voltage overscaled low-power digital filter IC. IEEE J. Solid State Circuits 39(2): 388-391 (2004)- 2002
- [b1]Rajamohana Hegde:
Reliable and Low -Power Signal Processing via Algorithmic Noise -Tolerance. University of Illinois Urbana-Champaign, USA, 2002 - 2001
- [j3]Rajamohana Hegde, Naresh R. Shanbhag:
Soft digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 813-823 (2001) - [c7]Rajamohana Hegde, Naresh R. Shanbhag:
A low-power digital filter IC via soft DSP. CICC 2001: 309-312 - 2000
- [j2]Rajamohana Hegde, Naresh R. Shanbhag:
Toward achieving energy efficiency in presence of deep submicron noise. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 379-391 (2000) - [c6]Rajamohana Hegde, Naresh R. Shanbhag:
Algorithmic noise-tolerance for low-power signal processing in the deep submicron era. EUSIPCO 2000: 1-4 - [c5]Rajamohana Hegde, Naresh R. Shanbhag:
Low-power digital filtering via soft DSP. ICASSP 2000: 3243-3246
1990 – 1999
- 1999
- [j1]Rajamohana Hegde, Naresh R. Shanbhag:
A low-power phase-splitting adaptive equalizer for high bit-rate communication systems. IEEE Trans. Signal Process. 47(3): 911-915 (1999) - [c4]Rajamohana Hegde, Naresh R. Shanbhag:
Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. ISCAS (6) 1999: 334-337 - [c3]Rajamohana Hegde, Naresh R. Shanbhag:
Energy-efficient signal processing via algorithmic noise-tolerance. ISLPED 1999: 30-35 - 1998
- [c2]Rajamohana Hegde, Naresh R. Shanbhag:
Energy-efficiency in presence of deep submicron noise. ICCAD 1998: 228-234 - 1995
- [c1]Rajamohana Hegde, B. A. Shenoi:
Design of 2-D IIR Filters Using a New Digital Spectral Transformation. ISCAS 1995: 344-347
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