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ORCIDTatsuya Hirose
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2010 – 2019
- 2013
[j8]Tatsuya Hirose, Tadahiro Taniguchi:
Abstraction Multimodal Low-Dimensional Representation from High-Dimensional Posture Information and Visual Images. J. Robotics Mechatronics 25(1): 80-88 (2013)- [c4]Hidekazu Suzuki, Katsuhiro Naito, Kazuma Kamienoo, Tatsuya Hirose, Akira Watanabe:
NTMobile: new end-to-end communication architecture in IPv4 and IPv6 networks. MobiCom 2013: 171-174 - 2012
- [j7]Ning Li, Keigo Bunsen
, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa:
A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 498-505 (2012) - 2010
- [c3]Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa:
A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. ESSCIRC 2010: 342-345
2000 – 2009
- 2009
- [j6]Masaru Sato, Tatsuya Hirose, Koji Mizuno:
Advanced MMIC Receiver for 94-GHz Band Passive Millimeter-Wave Imager. IEICE Trans. Electron. 92-C(9): 1124-1129 (2009) - [c2]Yoichi Kawano, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin:
A 77GHz transceiver in 90nm CMOS. ISSCC 2009: 310-311 - 2008
- [c1]Toshihide Suzuki, Yoichi Kawano, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin:
60 and 77GHz Power Amplifiers in Standard 90nm CMOS. ISSCC 2008: 562-563 - 2007
- [j5]Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose:
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology. IEEE J. Solid State Circuits 42(3): 637-646 (2007) - 2005
- [j4]Yusuke Inoue, Masaru Sato, Toshihiro Ohki, Kozo Makiyama, Tsuyoshi Takahashi, Hisao Shigematsu, Tatsuya Hirose:
A 90-GHz InP-HEMT lossy match amplifier with a 20-dB gain using a broadband matching technique. IEEE J. Solid State Circuits 40(10): 2098-2103 (2005) - 2004
- [j3]Toshihide Suzuki, Tsuyoshi Takahashi, Tatsuya Hirose, Masahiko Takikawa:
A 80-gbit/s D-type flip-flop circuit using InP HEMT technology. IEEE J. Solid State Circuits 39(10): 1706-1711 (2004) - 2002
- [j2]Hisao Shigematsu, Masaru Sato, Tatsuya Hirose, Yuu Watanabe:
A 54-GHz distributed amplifier with 6-VPP output for a 40-Gb/s LiNbO3 modulator driver. IEEE J. Solid State Circuits 37(9): 1100-1105 (2002) - [j1]Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe:
A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology. IEEE J. Solid State Circuits 37(12): 1703-1709 (2002)
Coauthor Index
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