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ORCIDYasuhiro Nakasha
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2020 – today
- 2024
[c6]Liang Zhou, Masafumi Tsutsui, Yasuhiro Nakasha, Shiro Ozaki, Takashi Dateki, Yusuke Kumazaki, Toshihiro Ohki:
Sub-THz SC-FDE MIMO Systems with Deep Neural Network Equalization for 100 Gbps of 6G. VTC Fall 2024: 1-5- 2023
- [j8]Yusuke Kumazaki, Shiro Ozaki, Naoya Okamoto, Naoki Hara, Yasuhiro Nakasha, Masaru Sato, Toshihiro Ohki:
High-Efficiency 250-320GHz Power Amplifiers Using InP-Based Metal-Oxide-Semiconductor High-Electron-Mobility Transistors. IEICE Trans. Electron. 106(11): 661-668 (2023) - 2022
- [c5]Tomoyuki Akiyama, Motoyuki Nishizawa, Akio Sugama, Yasuhiro Nakasha, Shinsuke Tanaka, Yu Tanaka, Takeshi Hoshida:
First Demonstration of Crosstalk-Free (< -38.5 dB) 32-ch DWDM Demultiplexer on Standard Si PIC Platform. OFC 2022: 1-3 - 2021
- [c4]Tomoyuki Akiyama, Motoyuki Nishizawa, Akio Sugama, Yasuhiro Nakasha, Shinsuke Tanaka, Yu Tanaka, Takeshi Hoshida:
Temperature-Tolerant Crosstalk-Free WDM Demultiplexing Using Controller-Integrated Cascaded AMZ Triplet (CAT) on Si Nano-Waveguide PIC Platform. ECOC 2021: 1-4 - [c3]Tomoyuki Akiyama, Motoyuki Nishizawa, Akio Sugama, Yasuhiro Nakasha, Shinsuke Tanaka, Yu Tanaka, Shoichiro Oda, Takeshi Hoshida:
Demonstration of Crosstalk-Free WDM Demultiplexing on Si Nanowire PIC Controlled by Si CMOS ASIC. OFC 2021: 1-3
2010 – 2019
- 2019
- [c2]Tomoyuki Akiyama, Shoichiro Oda, Seok-Hwan Jeong, Yasuhiro Nakasha, Yu Tanaka, Takeshi Hoshida
:
A Demultiplexer Immune from Fabrication-Error Impairments as an Enabler of Compact High-Channel-Count (> 64 ch) Dense WDM Systems on Low-End Si PIC Platforms. OECC/PSC 2019: 1-3 - 2017
- [j7]Masaru Sato, Yoshitaka Niida, Toshihide Suzuki, Yasuhiro Nakasha, Yoichi Kawano, Taisuke Iwai, Naoki Hara, Kazukiyo Joshin:
Robust Q-Band InP- and GaN-HEMT Low Noise Amplifiers. IEICE Trans. Electron. 100-C(5): 417-423 (2017) - 2016
- [j6]Hiroshi Matsumura, Yoichi Kawano, Shoichi Shiba, Masaru Sato, Toshihide Suzuki, Yasuhiro Nakasha, Tsuyoshi Takahashi, Kozo Makiyama, Taisuke Iwai, Naoki Hara:
300-GHz Amplifier in 75-nm InP HEMT Technology. IEICE Trans. Electron. 99-C(5): 528-534 (2016) - 2015
- [j5]Yasuhiro Nakasha:
Foreword. IEICE Trans. Electron. 98-C(12): 1058-1059 (2015) - [j4]Shoichi Shiba, Masaru Sato, Hiroshi Matsumura, Yoichi Kawano, Tsuyoshi Takahashi, Toshihide Suzuki, Yasuhiro Nakasha, Taisuke Iwai, Naoki Hara:
Beyond 110 GHz InP-HEMT Based Mixer Module Using Flip-Chip Assembly for Precise Spectrum Analysis. IEICE Trans. Electron. 98-C(12): 1112-1119 (2015) - 2013
- [c1]Masaru Sato, Shoichi Shiba, Hiroshi Matsumura, Tsuyoshi Takahashi, Toshihide Suzuki, Yasuhiro Nakasha, Naoki Hara:
Submillimeter-wave InP HEMT amplifiers with current-reuse topology. RWS 2013: 250-252 - 2011
- [j3]Yasuhiro Nakasha, Naoki Hara, Kiyomichi Araki:
Performance Analysis of a 10-Gb/s Millimeter-Wave Impulse Radio Transmitter. IEICE Trans. Electron. 94-C(10): 1557-1564 (2011)
2000 – 2009
- 2007
- [j2]Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose:
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology. IEEE J. Solid State Circuits 42(3): 637-646 (2007) - 2002
- [j1]Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Masahiko Takikawa, Yuu Watanabe:
A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology. IEEE J. Solid State Circuits 37(12): 1703-1709 (2002)
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