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ORCIDNam-Seog Kim
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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Other persons with the same name
- Nam-Seog Kim 0001
![[0000-0002-1039-5945]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-1039-5945")
— Chungbuk National University, Department of Information and Communication Engineering, School of Electrical and Computer Engineering, Korea (and 3 more)
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2010 – 2019
- 2016
[j4]Nam-Seog Kim, Byungkyu Park, Kang-Dae Lee:
A knowledge based freight management decision support system incorporating economies of scale: multimodal minimum cost flow optimization approach. Inf. Technol. Manag. 17(1): 81-94 (2016)- 2010
- [j3]Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun:
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. IEEE J. Solid State Circuits 45(1): 111-119 (2010)
2000 – 2009
- 2009
- [c5]Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology. ISSCC 2009: 130-131 - 2005
- [c4]Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application. CICC 2005: 533-536 - [c3]Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
A pseudo-differential CMOS receiver insensitive to input common mode level. ISCAS (1) 2005: 440-443 - 2004
- [j2]Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Synchronous mirror delay for multiphase locking. IEEE J. Solid State Circuits 39(1): 150-156 (2004) - 2003
- [j1]Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun:
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. IEEE J. Solid State Circuits 38(11): 1943-1951 (2003) - [c2]Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. CICC 2003: 391-394 - [c1]Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
New dynamic logic-level converters for high performance application. ISCAS (5) 2003: 93-96
Coauthor Index
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