"A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with ..."

Woo-Cheol Kim et al. (2019)

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DOI: 10.23919/VLSIC.2019.8778096

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-05

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Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, Seung-Tak Ryu:
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. VLSI Circuits 2019: 138-

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