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2020 – today
- 2022
[c4]Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho:
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. ISSCC 2022: 1-3- 2021
- [j4]Wanghua Wu
, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho:
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. IEEE J. Solid State Circuits 56(12): 3756-3767 (2021) - [c3]Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho:
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. ISSCC 2021: 444-446
2010 – 2019
- 2019
- [j3]Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. IEEE J. Solid State Circuits 54(5): 1254-1265 (2019) - 2014
- [j2]Zheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
A CMOS 210-GHz Fundamental Transceiver With OOK Modulation. IEEE J. Solid State Circuits 49(3): 564-580 (2014) - [j1]Pei-Yuan Chiang, Zheng Wang, Omeed Momeni, Payam Heydari:
A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range. IEEE J. Solid State Circuits 49(12): 2951-2963 (2014) - [c2]Pei-Yuan Chiang, Zheng Wang, Omeed Momeni, Payam Heydari:
14.7 A 300GHz frequency synthesizer with 7.9% locking range in 90nm SiGe BiCMOS. ISSCC 2014: 260-261 - 2013
- [c1]Zheng Wang, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen, Payam Heydari:
A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS. ISSCC 2013: 136-137
Coauthor Index
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