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2020 – today
- 2022
[c11]Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min
, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee:
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET. ESSCIRC 2022: 509-512- [c10]Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho:
A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. ISSCC 2022: 1-3 - 2021
- [j6]Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho:
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. IEEE J. Solid State Circuits 56(12): 3756-3767 (2021) - [c9]Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho:
32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. ISSCC 2021: 444-446
2010 – 2019
- 2019
- [j5]Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. IEEE J. Solid State Circuits 54(5): 1254-1265 (2019) - [j4]Jongwoo Lee, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ilyong Jong, Sanghyun Baek, Jae Hoon Lee, Ronghua Ni, Yongrong Zuo, Chih-Wei Yao, Seungchan Heo, Sangwook Han, Thomas Byunghak Cho, Inyup Kang, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Ji-Soo Chang, Sanghoon Kang:
A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 54(12): 3541-3552 (2019) - [c8]Jongwoo Lee, Sangwook Han, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Su-Seob Ahn, Sanghoon Kang, Quang-Diep Bui, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ronghua Ni, Yongrong Zuo, Ilyong Jong, Chih-Wei Yao, Seungchan Heo, Thomas Byunghak Cho, Inyup Kang:
A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS. ISSCC 2019: 354-356 - 2017
- [j3]Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. IEEE J. Solid State Circuits 52(12): 3446-3457 (2017) - [c7]Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. ISSCC 2017: 422-423 - 2013
- [j2]Chih-Wei Yao, Alan N. Willson Jr.:
A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO. IEEE J. Solid State Circuits 48(3): 698-710 (2013)
2000 – 2009
- 2009
- [j1]Jae Y. Kim, Chih-Wei Yao, Alan N. Willson Jr.:
A Programmable 25-MHz to 6-GHz Kvco Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 865-876 (2009) - [c6]Chih-Wei Yao, Alan N. Willson Jr.:
Frequency Synthesis with Arbitrary Input Clock Rate and Rational K/L Multiplier Ratio. ISCAS 2009: 1365-1368 - 2008
- [c5]Jae Y. Kim, Chih-Wei Yao, Alan N. Willson Jr.:
A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation. ISCAS 2008: 2629-2632 - 2006
- [c4]Chih-Wei Yao, Alan N. Willson Jr.:
Energy circulation quadrature LC-VCO. ISCAS 2006 - [c3]Chih-Wei Yao, Alan N. Willson Jr.:
A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion. ISSCC 2006: 701-710 - 2004
- [c2]Chih-Wei Yao, Hiep T. Pham, Alan N. Willson Jr.:
A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial data. CICC 2004: 155-158
1990 – 1999
- 1996
- [c1]Michael F. McNitt-Gray, Eric M. Hart, Jonathan G. Goldin, Chih-Wei Yao, Denise R. Aberle:
Pattern classification approach to characterizing solitary pulmonary nodules imaged on high-resolution computed tomography. Image Processing 1996
Coauthor Index
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