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2010 – 2019
- 2019
[j4]Wanghua Wu
, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho:
A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. IEEE J. Solid State Circuits 54(5): 1254-1265 (2019)- [j3]Jongwoo Lee, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ilyong Jong, Sanghyun Baek, Jae Hoon Lee, Ronghua Ni, Yongrong Zuo, Chih-Wei Yao, Seungchan Heo, Sangwook Han, Thomas Byunghak Cho, Inyup Kang, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Ji-Soo Chang, Sanghoon Kang:
A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 54(12): 3541-3552 (2019) - [c2]Jongwoo Lee, Sangwook Han, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Su-Seob Ahn, Sanghoon Kang, Quang-Diep Bui, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ronghua Ni, Yongrong Zuo, Ilyong Jong, Chih-Wei Yao, Seungchan Heo, Thomas Byunghak Cho, Inyup Kang:
A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS. ISSCC 2019: 354-356 - 2017
- [j2]Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. IEEE J. Solid State Circuits 52(12): 3446-3457 (2017) - [c1]Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. ISSCC 2017: 422-423 - 2016
- [j1]Siddharth Seth, Dae Hyun Kwon, Sriramkumar Venugopalan, Sang Won Son, Yongrong Zuo, Venumadhav Bhagavatula, Jaehyun Lim, Dongjin Oh, Thomas Byunghak Cho:
A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS. IEEE J. Solid State Circuits 51(5): 1096-1108 (2016)
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