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ORCIDMarios C. Papaefthymiou
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2010 – 2019
- 2018
[c64]Hsi-Shou Wu, Zhengya Zhang
, Marios C. Papaefthymiou:
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. ESSCIRC 2018: 162-165- [i2]Parker Hill, Babak Zamirai, Shengshuo Lu, Yu-Wei Chao, Michael Laurenzano, Mehrzad Samadi, Marios C. Papaefthymiou, Scott A. Mahlke, Thomas F. Wenisch, Jia Deng, Lingjia Tang, Jason Mars:
Rethinking Numerical Representations for Deep Neural Networks. CoRR abs/1808.02513 (2018) - 2017
- [c63]Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou:
A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices. A-SSCC 2017: 65-68 - [c62]Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou:
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. ISSCC 2017: 348-349 - 2016
- [j28]Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2068-2081 (2016) - [c61]Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou:
A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh. A-SSCC 2016: 133-136 - 2015
- [c60]Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. ASP-DAC 2015: 484-489 - [c59]Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou:
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. A-SSCC 2015: 1-4 - [c58]Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou:
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. VLSIC 2015: 246- - 2014
- [c57]Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou:
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. ISSCC 2014: 462-463 - 2013
- [j27]Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger:
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits 48(1): 140-149 (2013) - [j26]Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin:
Designing for Responsiveness with Computational Sprinting. IEEE Micro 33(3): 8-15 (2013) - [j25]Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin:
Utilizing Dark Silicon to Save Energy with Computational Sprinting. IEEE Micro 33(5): 20-28 (2013) - [c56]Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin:
Computational sprinting on a hardware/software testbed. ASPLOS 2013: 155-166 - 2012
- [j24]Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou:
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 977-988 (2012) - [c55]Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin:
Computational sprinting. HPCA 2012: 249-260 - [c54]Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger:
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC 2012: 68-70 - 2011
- [c53]Wei-Hsiang Ma, Jerry C. Kao, Marios C. Papaefthymiou:
A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. ESSCIRC 2011: 155-158 - 2010
- [j23]Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou:
187 MHz Subthreshold-Supply Charge-Recovery FIR. IEEE J. Solid State Circuits 45(4): 793-803 (2010)
2000 – 2009
- 2009
- [c52]Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou:
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. ESSCIRC 2009: 160-163 - [c51]Alexander T. Ishii, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou:
A resonant-clock 200MHz ARM926EJ-STM microcontroller. ESSCIRC 2009: 356-359 - 2008
- [j22]Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou:
Resonant-Clock Latch-Based Design. IEEE J. Solid State Circuits 43(4): 864-873 (2008) - 2007
- [j21]Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou:
Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits 42(1): 38-47 (2007) - [j20]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou:
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 586-590 (2007) - [c50]Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou:
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. CICC 2007: 583-586 - [c49]Zhengtao Yu, Marios C. Papaefthymiou, Xun Liu:
Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI 2007: 461-464 - [i1]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. CoRR abs/0710.4690 (2007) - 2006
- [j19]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 917-924 (2006) - [c48]Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou:
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC 2006: 777-780 - [c47]Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves:
Parallelizing post-placement timing optimization. IPDPS 2006 - 2005
- [j18]Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
Charge-Recovery Computing on Silicon. IEEE Trans. Computers 54(6): 651-659 (2005) - [j17]Xun Liu, Marios C. Papaefthymiou:
HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1089-1103 (2005) - [c46]Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou:
Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers 2005: 407-413 - [c45]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE 2005: 1330-1335 - [c44]Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler:
A GHz-class charge recovery logic. ISLPED 2005: 91-94 - [c43]Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler:
Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI 2005: 22-27 - [c42]Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler:
Two-Phase Resonant Clock Distribution. ISVLSI 2005: 65-70 - [c41]Jiyoun Kim, José Neves, Marios C. Papaefthymiou:
Multi-Session Partitioning for Parallel Timing Optimization. PDCAT 2005: 598-602 - 2004
- [j16]Xun Liu, Marios C. Papaefthymiou:
A Markov chain sequence generator for power macromodeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1048-1062 (2004) - [c40]Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
Practical repeater insertion for low power: what repeater library do we need? DAC 2004: 30-35 - [c39]Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab:
An Algorithm for Geometric Load Balancing with Two Constraints. IPDPS 2004 - [c38]Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou:
Empirical evaluation of timing and power in resonant clock distribution. ISCAS (2) 2004: 249-252 - [c37]Joohee Kim, Marios C. Papaefthymiou:
Constant-load energy recovery memory for efficient high-speed operation. ISLPED 2004: 240-243 - [c36]Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou:
Experimental Evaluation of Resonant Clock Distribution. ISVLSI 2004: 135-140 - [c35]Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky:
A synchronous interface for SoCs with multiple clock domains. SoCC 2004: 173-174 - [c34]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Clock tree layout design for reduced delay uncertainty. SoCC 2004: 179-180 - 2003
- [j15]Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
Fine-grain real-time reconfigurable pipelining. IBM J. Res. Dev. 47(5-6): 599-610 (2003) - [j14]Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
A true single-phase energy-recovery multiplier. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 194-207 (2003) - [j13]Xun Liu, Marios C. Papaefthymiou:
Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 965-975 (2003) - [j12]Joohee Kim, Marios C. Papaefthymiou:
Block-based multiperiod dynamic memory design for low data-retention power. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1006-1018 (2003) - [c33]Xun Liu, Marios C. Papaefthymiou:
HyPE: hybrid power estimation for IP-based programmable systems. ASP-DAC 2003: 606-609 - [c32]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075 - [c31]Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou:
A 225 MHz resonant clocked ASIC chip. ISLPED 2003: 48-53 - [c30]Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou:
Energy Recovering ASIC Design. ISVLSI 2003: 133-138 - 2002
- [j11]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Retiming and clock scheduling for digital circuit optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 184-203 (2002) - [c29]Xun Liu, Marios C. Papaefthymiou:
Design of a high-throughput low-power IS95 Viterbi decoder. DAC 2002: 263-268 - [c28]Xun Liu, Marios C. Papaefthymiou:
A Markov chain sequence generator for power macromodeling. ICCAD 2002: 404-411 - [c27]Xun Liu, Marios C. Papaefthymiou:
Incorporation of input glitches into power macromodeling. ISCAS (4) 2002: 846-849 - [c26]Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
Energy recovering static memory. ISLPED 2002: 92-97 - 2001
- [j10]Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou:
Symbolic debugging of embedded hardware and software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 392-401 (2001) - [j9]Suhwan Kim, Marios C. Papaefthymiou:
True single-phase adiabatic circuitry. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 52-63 (2001) - [c25]Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. ARVLSI 2001: 42-58 - [c24]Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
A True Single-Phase 8-bit Adiabatic Multiplier. DAC 2001: 758-763 - [c23]Xun Liu, Marios C. Papaefthymiou:
A static power estimation methodolodgy for IP-based design. DATE 2001: 280-289 - [c22]Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425 - [c21]Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou:
A resonant clock generator for single-phase adiabatic systems. ISLPED 2001: 159-164 - 2000
- [j8]Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak:
Optimizing computations for effective block-processing. ACM Trans. Design Autom. Electr. Syst. 5(3): 604-630 (2000) - [c20]Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou:
Symbolic debugging of globally optimized behavioral specifications. ASP-DAC 2000: 397-400 - [c19]Joohee Kim, Marios C. Papaefthymiou:
Dynamic Memory Design for Low Data-Retention Power. PATMOS 2000: 207-216
1990 – 1999
- 1999
- [j7]Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou:
Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors. Des. Autom. Embed. Syst. 4(4): 311-327 (1999) - [c18]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236 - [c17]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649 - [c16]Giuseppe Bernacchia, Marios C. Papaefthymiou:
Analytical macromodeling for high-level power estimation. ICCAD 1999: 280-283 - [c15]Suhwan Kim, Marios C. Papaefthymiou:
Single-phase source-coupled adiabatic logic. ISLPED 1999: 97-99 - 1998
- [c14]Marios C. Papaefthymiou:
Asymptotically efficient retiming under setup and hold constraints. ICCAD 1998: 396-401 - [c13]Suhwan Kim, Marios C. Papaefthymiou:
True single-phase energy-recovering logic for low-power, high-speed VLSI. ISLPED 1998: 167-172 - 1997
- [j6]Kumar N. Lalgudi, Marios C. Papaefthymiou:
Computing Strictly-Second Shortest Paths. Inf. Process. Lett. 63(4): 177-181 (1997) - [j5]Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou:
Optimizing two-phase, level-clocked circuitry. J. ACM 44(1): 148-199 (1997) - [j4]Kumar N. Lalgudi, Marios C. Papaefthymiou:
Retiming edge-triggered circuits under general delay models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12): 1393-1408 (1997) - [c12]Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante:
Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. JSSPP 1997: 277-298 - 1996
- [j3]Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou:
Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. Perform. Evaluation 27/28(4): 273-296 (1996) - [c11]Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak:
Optimizing Systems for Effective Block-Processing: The k-Delay Problem. DAC 1996: 714-719 - [c10]Marios C. Papaefthymiou, Kumar N. Lalgudi:
Fixed-phase retiming for low power design. ISLPED 1996: 259-264 - [c9]Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante:
A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. JSSPP 1996: 111-125 - [c8]Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou:
An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. SPAA 1996: 89-98 - 1995
- [c7]Kumar N. Lalgudi, Marios C. Papaefthymiou:
Efficient retiming under a general delay model. ARVLSI 1995: 368-382 - [c6]Kumar N. Lalgudi, Marios C. Papaefthymiou:
DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. DAC 1995: 304-309 - 1994
- [j2]Marios C. Papaefthymiou:
Understanding Retiming Through Maximum Avarage-Delay Cycles. Math. Syst. Theory 27(1): 65-84 (1994) - [j1]Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 426-436 (1994) - [c5]Marios C. Papaefthymiou, Joseph Rodrigue:
Implementing parallel shortest-paths algorithms. Parallel Algorithms 1994: 59-68 - [c4]Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81 - [c3]Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou:
Memory Assignment for Multiprocessor Caches through Grey Coloring. PARLE 1994: 351-362 - 1993
- [c2]Marios C. Papaefthymiou, Keith H. Randall:
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. DAC 1993: 497-502 - 1991
- [c1]Marios C. Papaefthymiou:
Understanding Retiming Through Maximum Average-Weight Cycles. SPAA 1991: 338-348
Coauthor Index
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