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2020 – today
- 2021
[c8]Nicky Lu, Chun Shiah, Juang-Ying Chueh, Bor-Doou Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, Chia-Wei Chang, Tzung-Shen Chen:
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns. VLSI Circuits 2021: 1-2
2010 – 2019
- 2013
- [c7]Juang-Ying Chueh, Chuck Tung:
Efficient standard cell abutment checker. ICECS 2013: 847-850
2000 – 2009
- 2007
- [j1]Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou:
Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits 42(1): 38-47 (2007) - 2006
- [c6]Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou:
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC 2006: 777-780 - [c5]Visvesh S. Sathe, Juang-Ying Chueh, Marios Papaefthymio:
A 1.1ghz charge-recovery logic. ISSCC 2006: 1540-1549 - 2005
- [c4]Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou:
Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers 2005: 407-413 - [c3]Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler:
Two-Phase Resonant Clock Distribution. ISVLSI 2005: 65-70 - 2004
- [c2]Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou:
Empirical evaluation of timing and power in resonant clock distribution. ISCAS (2) 2004: 249-252 - [c1]Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou:
Experimental Evaluation of Resonant Clock Distribution. ISVLSI 2004: 135-140
Coauthor Index
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