"Design Methodology for Synthesizing Resonant Clock Networks in the ..."

Seyong Ahn et al. (2016)

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DOI: 10.1109/TCAD.2016.2543022

access: closed

type: Journal Article

metadata version: 2020-09-24

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Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2068-2081 (2016)

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