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2010 – 2019
- 2016
[j5]Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox:
Carrizo: A High Performance, Energy Efficient 28 nm APU. IEEE J. Solid State Circuits 51(1): 105-116 (2016)- 2013
- [j4]Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger:
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits 48(1): 140-149 (2013) - 2012
- [j3]Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh:
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. IEEE J. Solid State Circuits 47(1): 164-176 (2012) - [c8]Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger:
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC 2012: 68-70 - 2011
- [c7]Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox:
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. ISSCC 2011: 78-80 - [c6]Michael Golden, Srikanth Arekapudi, James Vinh:
40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core. ISSCC 2011: 80-82
2000 – 2009
- 2006
- [c5]Michael Golden, Srikanth Arekapudi, Greg Dabney, Mike Haertel, Stephen Hale, Lowell Herlinger, Yongg Kim, Kevin McGrath, Vasant Palisetti, Monica Singh:
A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support. ISSCC 2006: 325-332 - 2005
- [j2]Srikanth Arekapudi, Shang-Tse Chuang, Isaac Keslassy
, Nick McKeown:
Using Hardware to Configure a Load-Balanced Switch. IEEE Micro 25(1): 70-78 (2005) - [c4]Srikanth Arekapudi, Echere Iroaga, Boris Murmann:
A low-power distributed wide-band LNA in 0.18µm CMOS. ISCAS (5) 2005: 5055-5058 - 2004
- [c3]Srikanth Arekapudi, Shang-Tse Chuang, Isaac Keslassy, Nick McKeown:
Configuring a load-balanced switch in hardware. Hot Interconnects 2004: 48-53 - 2003
- [j1]Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems. J. Circuits Syst. Comput. 12(3): 305-332 (2003) - 2002
- [c2]Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
ATPG for timing-induced functional errors on trigger events in hardware-software systems. ETW 2002: 23-28 - 2001
- [c1]Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
Test pattern generation for timing-induced functional errors in hardware-software systems. HLDVT 2001: 83-88
Coauthor Index
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