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2020 – today
- 2023
[c5]Prachi Shukla, Derrick Aguren, Tom Burd, Ayse K. Coskun, John Kalamatianos:
Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads. DATE 2023: 1-6- [c4]Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry R. Fair III, Dave Johnson, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim Jackson:
"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core. ISSCC 2023: 38-39
2010 – 2019
- 2017
- [j2]Sriram Sundaram
, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy:
Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. IEEE J. Solid State Circuits 52(1): 89-97 (2017) - 2016
- [j1]Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox:
Carrizo: A High Performance, Energy Efficient 28 nm APU. IEEE J. Solid State Circuits 51(1): 105-116 (2016) - [c3]Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger:
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. ISSCC 2016: 74-75
2000 – 2009
- 2009
- [c2]Richard Bartolotti, Tom Burd, Brian McMinn, Arun Chandra:
Constraint Management and Checking in Template-Based Circuit Designs. MTV 2009: 107-113 - 2008
- [c1]Weiqing Guo, Yu Zhong, Tom Burd:
Context-sensitive static transistor-level IR analysis. ICCAD 2008: 797-802
Coauthor Index
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