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"21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS."

Viki Szortyka et al. (2014)

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DOI: 10.1109/ISSCC.2014.6757472

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-10

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Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq:
21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS. ISSCC 2014: 366-367

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