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ORCIDDongsheng Yang 0002
Person information
- affiliation: Tokyo Institute of Technology, Department of Electrical and Electronic Engineering, Japan
Other persons with the same name
- Dongsheng Yang — disambiguation page
- Dongsheng Yang 0001
![[0000-0003-1262-5975]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-1262-5975")
— Northeastern University, School of Information Science and Engineering, Shenyang, China - Dongsheng Yang 0003 — Eindhoven University of Technology, Department of Electrical Engineering, AZ, Netherlands (and 2 more)
- Dongsheng Yang 0004 — Peking University, Department of Computer Science and Technology, Beijing, China
- Dongsheng Yang 0005 — National University of Defense Technology, Department of Management Science and Engineering, China
- Dongsheng Yang 0006 — Chinese Academy of Sciences, Shenyang Institute of Computing Technology, China
- Dongsheng Yang 0007 — Beihang University, Robotics Institute, School of Machanical Engineering and Automation, Beijing, China
- Dongsheng Yang 0008 — Beijing Jiaotong University, School of Mathematics and Statistics, China
- Dongsheng Yang 0009 — Kyoto University, Graduate School of Informatics, Japan (and 1 more)
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2010 – 2019
- 2018
[j5]Bangan Liu, Yun Wang, Jian Pang, Haosheng Zhang, Dongsheng Yang, Aravind Tharayil Narayanan, Dae Young Lee, Sung Tae Choi, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. IEICE Trans. Electron. 101-C(2): 126-134 (2018)- [c8]Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa:
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4 - 2017
- [j4]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. 100-C(3): 259-267 (2017) - [c7]Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC 2017: 13-14 - 2016
- [j3]Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. IEICE Trans. Electron. 99-C(6): 632-640 (2016) - [c6]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC 2016: 1-2 - [c5]Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC 2016: 197-200 - 2015
- [j2]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa:
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express 12(15): 20150531 (2015) - [j1]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits 50(1): 68-80 (2015) - [c4]Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC 2015: 2-3 - [c3]Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa:
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. ISSCC 2015: 1-3 - 2014
- [c2]Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa:
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. A-SSCC 2014: 285-288 - [c1]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. ISSCC 2014: 266-267
Coauthor Index
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