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ORCIDJunjun Qiu
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- affiliation: Tokyo Institute of Technology, Japan
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2020 – today
- 2025
[j10]Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Jill C. Mayeda, Atsushi Shirane, Kenichi Okada:
A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation. IEEE Access 13: 40210-40225 (2025)- [j9]Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada:
A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. IEEE J. Solid State Circuits 60(3): 1043-1055 (2025) - 2024
- [j8]Yuncheng Zhang
, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. IEEE J. Solid State Circuits 59(4): 993-1005 (2024) - [c11]Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. ISSCC 2024: 192-194 - 2023
- [c10]Dingxin Xu, Yuncheng Zhang, Hongye Huang, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany, Atsushi Shirane, Kenichi Okada:
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. CICC 2023: 1-2 - [c9]Waleed Madany, Yuncheng Zhang, Ashbir Aviat Fadila, Hongye Huang, Junjun Qiu, Atsushi Shirane, Kenichi Okada:
A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path. ESSCIRC 2023: 265-268 - [c8]Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. ISSCC 2023: 80-81 - [c7]Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu, Dongwon You, Hongye Huang, Waleed Madany, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j7]Junjun Qiu, Bangan Liu, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada:
A low-power digital baseband circuit for GMSK demodulation in sub-GHz application. IEICE Electron. Express 19(12): 20220201 (2022) - [j6]Yuncheng Zhang, Bangan Liu, Teruki Someya, Rui Wu, Junjun Qiu, Atsushi Shirane, Kenichi Okada:
A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components. IEICE Trans. Electron. 105-C(7): 334-342 (2022) - [j5]Yun Wang, Dongwon You, Xi Fu, Takeshi Nakamura, Ashbir Aviat Fadila, Teruki Someya, Atsuhiro Kawaguchi, Junjun Qiu, Jian Pang, Kiyoshi Yanagisawa, Bangan Liu, Yuncheng Zhang, Haosheng Zhang, Rui Wu, Shunichiro Masaki, Daisuke Yamazaki, Atsushi Shirane, Kenichi Okada:
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. IEEE J. Solid State Circuits 57(2): 356-370 (2022) - 2021
- [j4]Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Jian Pang, Hanli Liu, Masaya Miyahara, Atsushi Shirane, Kenichi Okada:
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. IEEE J. Solid State Circuits 56(12): 3741-3755 (2021) - [j3]Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Aravind Tharayil Narayanan, Haosheng Zhang, Teruki Someya, Atsushi Shirane, Kenichi Okada:
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 603-616 (2021) - [c6]Zheng Sun, Dingxin Xu, Junjun Qiu, Zezheng Liu, Yuncheng Zhang, Hongye Huang, Hanli Liu, Bangan Liu, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. ESSCIRC 2021: 499-502 - [c5]Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Atsushi Shirane, Kenichi Okada:
32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. ISSCC 2021: 454-456 - 2020
- [j2]Yun Wang, Rui Wu, Jian Pang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Xi Fu, Daiki Matsumoto, Takeshi Nakamura, Ryo Kubozoe, Masaru Kawabuchi, Bangan Liu, Haosheng Zhang, Junjun Qiu, Hanli Liu, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS. IEEE J. Solid State Circuits 55(5): 1249-1269 (2020) - [j1]Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Bangan Liu, Aravind Tharayil Narayanan, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. IEEE J. Solid State Circuits 55(9): 2371-2386 (2020) - [c4]Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Kiyoshi Yanagisawa, Junjun Qiu, Yun Wang, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c3]Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada:
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC 2019: 1-4 - [c2]Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You, Ashbir Aviat Fadila, Rattanan Saengchan, Takeshi Nakamura, Joshua Alvin, Daiki Matsumoto, Aravind Tharayil Narayanan, Bangan Liu, Junjun Qiu, Hanli Liu, Zheng Sun, Hongye Huang, Korkut Kaan Tokgoz, Keiichi Motoi, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada:
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. ISSCC 2019: 344-346 - 2018
- [c1]Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa:
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4
Coauthor Index
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