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2020 – today
- 2024
[j3]Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi:
A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(5): 709-718 (2024)- 2022
- [c4]Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi:
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. ESSCIRC 2022: 505-508 - 2021
- [j2]Bangan Liu
, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Aravind Tharayil Narayanan, Haosheng Zhang, Teruki Someya, Atsushi Shirane, Kenichi Okada:
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 603-616 (2021)
2010 – 2019
- 2018
- [j1]Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada:
A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. IEEE J. Solid State Circuits 53(12): 3540-3552 (2018) - [c3]Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa:
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4 - [c2]Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa:
A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. ISSCC 2018: 246-248 - 2017
- [c1]Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa:
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. ISSCC 2017: 150-151
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