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ORCIDSatoshi Takaya
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2020 – today
- 2020
[c9]Satoshi Takaya, Hiroaki Ishihara, Kohei Onizuka:
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics. ISSCC 2020: 298-300
2010 – 2019
- 2019
- [c8]Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami:
Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications. VLSI Circuits 2019: 278- - 2018
- [j8]Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama:
SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. IEICE Electron. Express 15(3): 20171232 (2018) - [c7]Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi:
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. ISCAS 2018: 1-5 - 2017
- [j7]Tetsufumi Tanamoto
, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita:
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 827-831 (2017) - [i3]Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani:
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR abs/1703.00073 (2017) - [i2]Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama:
SPICE Simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. CoRR abs/1710.07375 (2017) - 2016
- [c6]Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC 2016: 132-133 - [i1]Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita:
Physically Unclonable Function using Initial Waveform of Ring Oscillators. CoRR abs/1605.03290 (2016) - 2015
- [j6]Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda:
In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking. IEEE Des. Test 32(6): 87-98 (2015) - [c5]Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita:
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC 2015: 1-3 - 2014
- [j5]Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata:
Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking. IEICE Trans. Electron. 97-C(6): 557-565 (2014) - [c4]Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata:
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC 2014: 216-217 - 2013
- [j4]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. IEICE Trans. Electron. 96-C(6): 884-893 (2013) - [c3]Satoshi Takaya, Makoto Nagata, Hiroaki Ikeda:
Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs. 3DIC 2013: 1-4 - [c2]Satoshi Takaya, Makoto Nagata, Atsushi Sakai, Takashi Kariya, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda:
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. ISSCC 2013: 434-435 - 2012
- [j3]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. IEICE Trans. Electron. 95-C(1): 137-145 (2012) - 2011
- [j2]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Trans. Electron. 94-C(4): 495-503 (2011) - [j1]Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Trans. Electron. 94-C(6): 1024-1031 (2011) - [c1]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED 2011: 56-61
Coauthor Index
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