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ORCIDShigetaka Kumashiro
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2020 – today
- 2023
[c8]Kazutoshi Kobayashi, Tomoharu Kishita, Hiroki Nakano, Jun Furuta, Mitsuhiko Igarashi, Shigetaka Kumashiro, Michitarou Yabuuchi, Hironori Sakamoto:
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. IRPS 2023: 1-7- 2020
- [j12]Shigetaka Kumashiro
, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi:
An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 451-463 (2020)
2010 – 2019
- 2013
- [j11]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. IEICE Trans. Electron. 96-C(6): 884-893 (2013) - [c7]Shigetaka Kumashiro:
A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistors. ISQED 2013: 391-397 - 2012
- [j10]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. IEICE Trans. Electron. 95-C(1): 137-145 (2012) - [c6]Hironori Sakamoto, Shigetaka Kumashiro, Shigeo Sato, Naoki Wakita, Tohru Mogami:
HiSIM-RP: A reverse-profiling based 1st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS. ISQED 2012: 553-560 - 2011
- [j9]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Trans. Electron. 94-C(4): 495-503 (2011) - [j8]Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Trans. Electron. 94-C(6): 1024-1031 (2011) - [c5]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED 2011: 56-61 - 2010
- [j7]Kenta Yamada, Toshiyuki Syo, Hisao Yoshimura, Masaru Ito, Tatsuya Kunikiyo, Toshiki Kanamoto, Shigetaka Kumashiro:
Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns. IEICE Trans. Electron. 93-C(8): 1349-1358 (2010)
2000 – 2009
- 2008
- [j6]Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro:
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Trans. Electron. 91-C(7): 1142-1150 (2008) - [j5]Tatsuya Ezaki, Dondee Navarro, Youichi Takeda, Norio Sadachika, Gaku Suzuki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto:
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. Math. Comput. Simul. 79(4): 1096-1106 (2008) - 2005
- [j4]Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. IEICE Trans. Electron. 88-C(2): 247-254 (2005) - [j3]Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. IEICE Trans. Electron. 88-C(5): 1079-1086 (2005) - [c4]Youichi Takeda, Dondee Navarro, Shingo Chiba, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto:
MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. CICC 2005: 827-830 - 2003
- [c3]Kazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. ASP-DAC 2003: 179-183 - 2002
- [j2]Mitiko Miura-Mattausch, Hiroaki Ueno, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Circuit Simulation Models for Coming MOSFET Generations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 740-748 (2002) - 2001
- [c2]D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Correlation method of circuit-performance and technology fluctuations for improved design reliability. ASP-DAC 2001: 39-44 - [c1]Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. CICC 2001: 357-360
1990 – 1999
- 1993
- [j1]Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas:
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 988-996 (1993)
Coauthor Index
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