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ORCIDTakeshi Ogura
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2010 – 2019
- 2019
[c21]Takeshi Kumaki, Tomohiro Fujita, Takeshi Ogura, P. S. Venugopala:
Distributed Embedding Approach for Max-Plus Algebra-Based Morphological Wavelet Transform Watermarking. NEWCAS 2019: 1-4- 2014
- [j14]Takeshi Kumaki, Kei Nakao, Kohei Hozumi, Takeshi Ogura, Takeshi Fujino:
Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices. IEICE Trans. Inf. Syst. 97-D(3): 593-596 (2014) - [c20]Hiroshi Morita, Koki Uchino, Eiji Otani, Hiizu Ohtorii, Takeshi Ogura, Kazunao Oniki, Shuichi Oka, Shusaku Yanagawa, Hideyuki Suzuki:
8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS. ISSCC 2014: 140-141 - [c19]Tomohiro Fujita, Syo Sawada, Kaihei Iwanaga, Takeshi Kumaki, Mamoru Nakanishi, Takeshi Ogura:
Cellular automaton based pixel-level snakes. NEWCAS 2014: 393-396 - 2013
- [c18]Kosaku Fukuda, Lin Meng
, Takeshi Kumaki, Takeshi Ogura:
A CAM-Based Separated BTB for a Superscalar Processor. CANDAR 2013: 385-388 - [c17]Kei Nakao, Kohei Hozumi, Takeshi Kumaki, Takeshi Ogura, Takeshi Fujino:
Development of effective information-hiding method for embedded systems. MWSCAS 2013: 1298-1301 - [c16]Matsui Takao, Tomohiro Fujita, Tsuji Yuji, Takeshi Kumaki, Mamoru Nakanishi, Takeshi Ogura:
Evaluation of advanced pixel-level snakes on cellular hardware platform. NEWCAS 2013: 1-4 - 2010
- [c15]Kenichi Maruko, Tatsuya Sugioka, Hiroaki Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Yuki Yagishita, Hironobu Konishi, Toshikyuki Ogata, Hisashi Owa, Taichi Niki, Kenji Konda, Masahiro Sato, Hiro Shiroshita, Takeshi Ogura, Takayuki Aoki, Hiroki Kihara, Sachiya Tanaka:
A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator. ISSCC 2010: 364-365
2000 – 2009
- 2002
- [j13]Mahmoud Méribout, Mamoru Nakanishi, Takeshi Ogura:
A parallel algorithm for real-time object recognition. Pattern Recognit. 35(9): 1917-1931 (2002) - [j12]Mahmoud Méribout, Mamoru Nakanishi, Takeshi Ogura:
Accurate and Real-time Image Processing on a New PC-compatible Board. Real Time Imaging 8(1): 35-51 (2002) - [j11]Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Takeshi Ogura:
Advanced concurrent design environment for multimedia system LSIs. Syst. Comput. Jpn. 33(14): 72-80 (2002) - 2000
- [j10]Mahmoud Méribout, Mamoru Nakanishi, Eiichi Hosoya, Takeshi Ogura:
Hough Transform Algorithm for Three-Dimensional Segment Extraction and its Parallel Hardware Implementation. Comput. Vis. Image Underst. 78(2): 177-205 (2000) - [j9]Takeshi Ikenaga, Takeshi Ogura:
A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing. IEEE J. Solid State Circuits 35(4): 536-544 (2000) - [j8]Mamoru Nakanishi, Takeshi Ogura:
Real-time CAM-based Hough transform algorithm and its performance evaluation. Mach. Vis. Appl. 12(2): 59-68 (2000) - [j7]Takeshi Ikenaga, Takeshi Ogura:
Real-time morphology processing using highly parallel 2-D cellular automata CAM2. IEEE Trans. Image Process. 9(12): 2018-2026 (2000) - [j6]Mahmoud Méribout, Takeshi Ogura, Mamoru Nakanishi:
On using the CAM concept for parametric curve extraction. IEEE Trans. Image Process. 9(12): 2126-2130 (2000) - [c14]Tetsuo Sawaragi, Takeshi Ogura:
Concept sharing between human and interface agent under time criticality. Advanced Network Enterprises 2000: 269-278 - [c13]Ken Nakamura, Mitsuo Ikeda, Takeshi Yoshitome, Takeshi Ogura:
Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System. ITCC 2000: 195-200
1990 – 1999
- 1999
- [j5]Mahmoud Méribout, Mamoru Nakanishi, Takeshi Ogura:
A Real-Time Image Segmentation on a Massively Parallel Architecture. Real Time Imaging 5(4): 279-291 (1999) - [c12]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura:
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. DATE 1999: 44- - [c11]Katsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura:
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit. DATE 1999: 303-308 - [c10]Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura:
On-Chip Multimedia Real-Time OS and its MPEG-2 Applications. RTCSA 1999: 200-203 - 1998
- [j4]Takeshi Ikenaga, Takeshi Ogura:
CAM2: A Highly-Parallel Two-Dimensional Cellular Architecture. IEEE Trans. Computers 47(7): 788-801 (1998) - [c9]Eiichi Hosoya, Mamoru Nakanishi, Takeshi Ogura:
Real-time 3D Reconstruction System using CAM-based Highly Parallel Processing Board. Three-Dimensional Image Capture and Applications 1998: 159-167 - 1997
- [c8]Takeshi Ikenaga, Takeshi Ogura:
Real-Time Morphology Processing Using Highly Parallel 2D Cellular Automata CAM2. ICIP (2) 1997: 562-565 - [c7]Mamoru Nakanishi, Takeshi Ogura:
Real-Time Line Extraction Using a Highly Parallel Hough Tranform Board. ICIP (2) 1997: 582-585 - 1996
- [c6]Takeshi Ikenaga, Takeshi Ogura:
CAM²: A Highly-Parallel 2D Cellular Automata Architecture for Real-Time and Palm-Top Pixel-Level Image Processing. Euro-Par, Vol. II 1996: 203-212 - [c5]Mamoru Nakanishi, Takeshi Ogura:
A real-time CAM-based Hough transform algorithm and its performance evaluation. ICPR 1996: 516-521 - [c4]Mahmoud Méribout, Takeshi Ogura, Mamoru Nakanishi:
Real-time Hough Transform Based Circular Shape Extraction. MVA 1996: 178-182 - [c3]Eiichi Hosoya, Takeshi Ogura, Mamoru Nakanishi:
Real-time 3D Feature Extraction Hardware Algorithm with Feature Point Matching Capability. MVA 1996: 430-433 - 1994
- [j3]Jiro Naganuma, Takeshi Ogura:
A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms. IEEE Trans. Computers 43(9): 1062-1075 (1994) - [c2]Jiro Naganuma, Takeshi Ogura, Tamio Hoshino:
High-Level Design Validation Using Algorithmic Debugging. EDAC-ETC-EUROASIC 1994: 474-480 - 1993
- [c1]Yuichi Fujino, Takeshi Ogura, Toshiaki Tsuchiya:
Facial image tracking system architecture utilizing real-time labeling. VCIP 1993
1980 – 1989
- 1989
- [j2]Takeshi Ogura, Junzo Yamada, Shin-Ichiro Yamada, Masa'aki Tan'no:
A 20 kbit associative memory LSI for artificial intelligence machines. IEEE J. Solid State Circuits 24(4): 1014-1020 (1989) - 1988
- [j1]Jiro Naganuma, Takeshi Ogura, Shin-Ichiro Yamada, Takashi Kimura:
High-Speed CAM-Based Architecture for a Prolog Machine (ASCA). IEEE Trans. Computers 37(11): 1375-1383 (1988)
Coauthor Index
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