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ORCIDMamoru Nakanishi
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2010 – 2019
- 2015
[j14]Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. IEICE Trans. Electron. 98-C(1): 45-52 (2015)- 2014
- [j13]Ryota Takasu, Yoichi Tomioka
, Yutaro Ishigaki, Ning Li, Tsugumichi Shibata, Mamoru Nakanishi, Hitoshi Kitazawa:
An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU. IEICE Trans. Electron. 97-C(7): 697-706 (2014) - [c13]Tomohiro Fujita, Syo Sawada, Kaihei Iwanaga, Takeshi Kumaki, Mamoru Nakanishi, Takeshi Ogura:
Cellular automaton based pixel-level snakes. NEWCAS 2014: 393-396 - 2013
- [c12]Matsui Takao, Tomohiro Fujita, Tsuji Yuji, Takeshi Kumaki, Mamoru Nakanishi, Takeshi Ogura:
Evaluation of advanced pixel-level snakes on cellular hardware platform. NEWCAS 2013: 1-4 - 2012
- [c11]Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs. ISCAS 2012: 1464-1467 - 2011
- [c10]Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON. A-SSCC 2011: 305-308 - [c9]Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata:
10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control. ISOCC 2011: 357-360 - 2010
- [j12]Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida:
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. IEEE J. Solid State Circuits 45(5): 1080-1087 (2010)
2000 – 2009
- 2008
- [c8]Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi:
A Fingerprint Sensor with Impedance Sensing for Fraud Detection. ISSCC 2008: 170-171 - 2007
- [j11]Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi:
Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Trans. Electron. 90-C(10): 1892-1899 (2007) - 2006
- [j10]Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi:
Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. 89-C(4): 540-550 (2006) - 2005
- [j9]Mahmoud Méribout, Mamoru Nakanishi:
A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture. J. VLSI Signal Process. 39(3): 249-266 (2005) - 2004
- [j8]Mahmoud Méribout, Lazhar Khriji, Mamoru Nakanishi:
A robust hardware algorithm for real-time object tracking in video sequences. Real Time Imaging 10(3): 145-159 (2004) - 2002
- [j7]Mahmoud Méribout, Mamoru Nakanishi, Takeshi Ogura:
A parallel algorithm for real-time object recognition. Pattern Recognit. 35(9): 1917-1931 (2002) - [j6]Mahmoud Méribout, Mamoru Nakanishi, Takeshi Ogura:
Accurate and Real-time Image Processing on a New PC-compatible Board. Real Time Imaging 8(1): 35-51 (2002) - [c7]Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi:
A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. CICC 2002: 261-264 - [c6]Namiko Ikeda, Mamoru Nakanishi, Koji Fujii, Takahiro Hatano, Satoshi Shigematsu, Takuya Adachi, Yukio Okazaki, Hakaru Kyuragi:
Fingerprint Image Enhancement by Pixel-Parallel Processing. ICPR (3) 2002: 752-755 - 2000
- [j5]Mahmoud Méribout, Mamoru Nakanishi, Eiichi Hosoya, Takeshi Ogura:
Hough Transform Algorithm for Three-Dimensional Segment Extraction and its Parallel Hardware Implementation. Comput. Vis. Image Underst. 78(2): 177-205 (2000) - [j4]Mamoru Nakanishi, Takeshi Ogura:
Real-time CAM-based Hough transform algorithm and its performance evaluation. Mach. Vis. Appl. 12(2): 59-68 (2000) - [j3]Mahmoud Méribout, Takeshi Ogura, Mamoru Nakanishi:
On using the CAM concept for parametric curve extraction. IEEE Trans. Image Process. 9(12): 2126-2130 (2000)
1990 – 1999
- 1999
- [j2]Mahmoud Méribout, Mamoru Nakanishi, Takeshi Ogura:
A Real-Time Image Segmentation on a Massively Parallel Architecture. Real Time Imaging 5(4): 279-291 (1999) - 1998
- [c5]Eiichi Hosoya, Mamoru Nakanishi, Takeshi Ogura:
Real-time 3D Reconstruction System using CAM-based Highly Parallel Processing Board. Three-Dimensional Image Capture and Applications 1998: 159-167 - 1997
- [c4]Mamoru Nakanishi, Takeshi Ogura:
Real-Time Line Extraction Using a Highly Parallel Hough Tranform Board. ICIP (2) 1997: 582-585 - 1996
- [c3]Mamoru Nakanishi, Takeshi Ogura:
A real-time CAM-based Hough transform algorithm and its performance evaluation. ICPR 1996: 516-521 - [c2]Mahmoud Méribout, Takeshi Ogura, Mamoru Nakanishi:
Real-time Hough Transform Based Circular Shape Extraction. MVA 1996: 178-182 - [c1]Eiichi Hosoya, Takeshi Ogura, Mamoru Nakanishi:
Real-time 3D Feature Extraction Hardware Algorithm with Feature Point Matching Capability. MVA 1996: 430-433 - 1995
- [j1]Mamoru Nakanishi:
Improved reslicing by voxel-project-method. Syst. Comput. Jpn. 26(4): 20-29 (1995)
Coauthor Index
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