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2020 – today
- 2023
[j4]Brian T. Vanderpool
, Phillip J. Restle, Eric Fluhr, Gregory S. Still, Francesco A. Campisano, Ian Charmichael, Eric Marz, Rahul Batra, Richard L. Willaman:
Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. IEEE J. Solid State Circuits 58(1): 102-110 (2023)- 2022
- [c5]Brian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman:
Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. ISSCC 2022: 1-3
2010 – 2019
- 2015
- [j3]Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny:
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59(1) (2015) - [j2]Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50(1): 10-23 (2015) - 2014
- [c4]Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor:
The POWER8TM processor: Designed for big data, analytics, and cloud environments. ICICDT 2014: 1-4 - [c3]Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler:
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC 2014: 96-97 - [c2]Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich:
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. ISSCC 2014: 98-99 - [c1]Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich:
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. ISSCC 2014: 100-101
1990 – 1999
- 1996
- [j1]James W. Bishop, Michael J. Campion, Thomas L. Jeremiah, Stephen J. Mercier, Edmond J. Mohring, Kerry P. Pfarr, Bruce G. Rudolph, Gregory S. Still, Tennis S. White:
PowerPC AS A10 64-bit RISC microprocessor. IBM J. Res. Dev. 40(4): 495-506 (1996)
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