"15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable ..."

Ahmed Elkholy et al. (2014)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2014.6757431

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/ElkholyESSH14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/ElkholyESSH14
Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu:
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. ISSCC 2014: 272-273

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.