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2020 – today
- 2025
[j23]Ladan Sayadi, Abdolah Amirany, Mohammad Hossein Moaiyeri, Somayeh Timarchi:
Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications. J. Supercomput. 81(1): 109 (2025)- 2023
- [j22]Mohammad Mehdi Gilanian Sadeghi, Somayeh Timarchi
, Mahmood Fazlali:
High-Performance Memory Allocation on FPGA With Reduced Internal Fragmentation. IEEE Access 11: 66672-66681 (2023) - [j21]Ladan Sayadi, Somayeh Timarchi, Akbar Sheikh-Akbari:
Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1649-1659 (2023) - [j20]Mina Raouf, Somayeh Timarchi:
Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2236-2240 (2023) - 2022
- [j19]Seyed Amir Hossein Ejtahed, Somayeh Timarchi:
Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor. Circuits Syst. Signal Process. 41(5): 2699-2718 (2022) - [j18]Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid:
Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization. Microprocess. Microsystems 93: 104588 (2022) - [j17]Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid:
Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 5079-5083 (2022) - 2021
- [j16]Ahmad Shabani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Somayeh Timarchi:
Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1259-1268 (2021) - 2020
- [j15]Hossein Mahdavi, Somayeh Timarchi:
Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2297-2304 (2020)
2010 – 2019
- 2019
- [j14]Somayeh Timarchi, Negar Akbarzadeh:
Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n - 1 Adder and Multiplier. Circuits Syst. Signal Process. 38(5): 2138-2164 (2019) - [j13]Adib Armand, Somayeh Timarchi, Hossein Mahdavi:
Optimized Parity-Based Error Detection and Correction Methods for Residue Number System. J. Circuits Syst. Comput. 28(1): 1950002:1-1950002:15 (2019) - [j12]Ahmad Shabani, Somayeh Timarchi, Hossein Mahdavi:
Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix. Microelectron. J. 91: 11-21 (2019) - [j11]Hossein Mahdavi, Somayeh Timarchi:
Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3874-3881 (2019) - 2018
- [j10]Hamed Naseri, Somayeh Timarchi:
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1481-1493 (2018) - 2017
- [j9]Ahmad Shabani, Somayeh Timarchi:
Low-power DCT-based compressor for wireless capsule endoscopy. Signal Process. Image Commun. 59: 83-95 (2017) - 2016
- [j8]Majid Moghaddam, Somayeh Timarchi, Mohammad Hossein Moaiyeri, Mohammad Eshghi:
An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques. Circuits Syst. Signal Process. 35(5): 1437-1455 (2016) - [j7]Masoud Abbasi Alaie, Somayeh Timarchi:
Efficient modulo 2n +1 multiplier. Int. J. Comput. Aided Eng. Technol. 8(3): 260-276 (2016) - [c6]Somayeh Timarchi, Massimo Alioto:
Ultra-low voltage standard cell libraries: Design strategies and a case study. ICECS 2016: 520-523 - 2015
- [j6]Mahmood Fazlali, Hadi Valikhani, Somayeh Timarchi, Hadi Tabatabaee Malazi:
Fast architecture for decimal digit multiplication. Microprocess. Microsystems 39(4-5): 296-301 (2015) - 2014
- [c5]Ardalan Najafi, Somayeh Timarchi, Amir Najafi:
High-speed energy-efficient 5: 2 compressor. MIPRO 2014: 80-84 - 2013
- [c4]Somayeh Timarchi, Maryam Saremi, Mahmood Fazlali, Georgi Gaydadjiev:
High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding. VLSI-SoC 2013: 58-59 - 2012
- [j5]Somayeh Timarchi, Mahmood Fazlali:
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n - 1, 2n, 2n + 1}. IET Comput. Digit. Tech. 6(5): 269-276 (2012) - 2010
- [j4]Amir Sabbagh Molahosseini, Keivan Navi, Chitra Dadkhah, Omid Kavehei, Somayeh Timarchi:
Efficient Reverse Converter Designs for the New 4-Moduli Sets 2n -1, 2n, 2n +1, 22n + 1-1 and 2n -1, 2n +1, 22n, 22n +1 Based on New CRTs. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(4): 823-835 (2010) - [c3]Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana:
A unified addition structure for moduli set {2n-1, 2n, 2n+1} based on a novel RNS representation. ICCD 2010: 247-252
2000 – 2009
- 2009
- [j3]Somayeh Timarchi, Keivan Navi:
A new algorithm for determining all possible symmetric hybrid redundant numbers. IEICE Electron. Express 6(1): 8-13 (2009) - [j2]Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehei:
A novel low-power full-adder cell for low voltage. Integr. 42(4): 457-467 (2009) - [j1]Somayeh Timarchi, Keivan Navi:
Arithmetic Circuits of Redundant SUT-RNS. IEEE Trans. Instrum. Meas. 58(9): 2959-2968 (2009) - [c2]Somayeh Timarchi, Keivan Navi, Omid Kavehei:
Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation. ISVLSI 2009: 97-102 - 2005
- [c1]Somayeh Timarchi, Seyed Ghassem Miremadi, Ali Reza Ejlali:
Evaluation of Some Exponential Random Number Generators Implemented by FPGA. Parallel and Distributed Computing and Networks 2005: 578-583
Coauthor Index
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