"Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - ..."

David Esseni et al. (2014)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2013.2293135

access: closed

type: Journal Article

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/EsseniGKRA14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/EsseniGKRA14
David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, Massimo Alioto:
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2488-2498 (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.