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2020 – today
- 2024
[j6]Xiaoyu Sun
, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang:
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1191-1205 (2024)- [c9]Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. ISSCC 2024: 572-574 - 2023
- [j5]Kerem Akarvardar, H.-S. Philip Wong:
Technology Prospects for Data-Intensive Computing. Proc. IEEE 111(1): 92-112 (2023) - [c8]Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. ISSCC 2023: 132-133 - 2022
- [c7]Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. ISSCC 2022: 1-3 - 2021
- [j4]Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang:
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. IEEE J. Solid State Circuits 56(1): 188-198 (2021) - [c6]Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Cheng Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang:
An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. ISSCC 2021: 252-254 - 2020
- [j3]H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin:
A Density Metric for Semiconductor Technology [Point of View]. Proc. IEEE 108(4): 478-482 (2020) - [j2]H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri:
Scanning the Issue. Proc. IEEE 108(4): 483-484 (2020)
2010 – 2019
- 2010
- [c5]Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Efficient FPGAs using nanoelectromechanical relays. FPGA 2010: 273-282
2000 – 2009
- 2009
- [c4]Soogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong:
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage. ICCAD 2009: 478-484 - 2007
- [j1]Kerem Akarvardar, Abdelkarim Mercha, Eddy Simoen, Vaidyanathan Subramanian, Cor Claeys, Pierre Gentil, Sorin Cristoloveanu:
High-temperature performance of state-of-the-art triple-gate transistors. Microelectron. Reliab. 47(12): 2065-2069 (2007) - 2005
- [c3]Suheng Chen, James Vandersand, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Mohammad M. Mojarradi:
SOI four-gate transistors (G4-FETs) for high voltage analog applications. ESSCIRC 2005: 311-314 - [c2]Kerem Akarvardar, Suheng Chen, Benjamin J. Blalock, Sorin Cristoloveanu, Pierre Gentil, Mohammad M. Mojarradi:
A novel four-quadrant analog multiplier using SOI four-gate transistors (G4-FETs). ESSCIRC 2005: 499-502 - [c1]Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil:
The G4-FET: a universal and programmable logic gate. ACM Great Lakes Symposium on VLSI 2005: 349-352
Coauthor Index
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