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2010 – 2019
- 2015
[j3]Szu-Chi Chung
, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 88-97 (2015)- 2014
- [j2]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 49-61 (2014) - 2013
- [c6]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Processor with side-channel attack resistance. ISSCC 2013: 50-51 - 2012
- [j1]Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 287-291 (2012) - [c5]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. CHES 2012: 548-564 - [c4]Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. ISCAS 2012: 1456-1459 - [c3]Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee:
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. VLSIC 2012: 156-157 - 2011
- [c2]Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. ISCAS 2011: 713-716 - 2010
- [c1]Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee:
A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance. ESSCIRC 2010: 206-209
Coauthor Index
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