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2020 – today
- 2020
[c6]Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang:
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. DATE 2020: 891-896
2010 – 2019
- 2011
- [c5]Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang
, Jing-Yang Jou:
Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC 2011: 497-502 - 2010
- [j2]Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou:
FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010)
2000 – 2009
- 2009
- [j1]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 723-727 (2009) - 2006
- [c4]Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453 - 2005
- [c3]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. HLDVT 2005: 87-93 - 2004
- [c2]Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou:
On compliance test of on-chip bus for SOC. ASP-DAC 2004: 328-333 - 2003
- [c1]Che-Hua Shih, Jing-Yang Jou:
An efficient approach for error diagnosis in HDL design. ISCAS (4) 2003: 732-735
Coauthor Index
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