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ORCIDHiroaki Shikano
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2010 – 2019
- 2017
[c6]Hiroaki Shikano, Takeshi Shibata, Qifeng Shen, Miyuki Hanaoka, Mariko Miyaki, Masahide Ban, Prasad Rallapalli, Yukinori Sakashita:
QoS Analysis on Cable Video Delivery Networks. DCNET 2017: 85-92- 2013
- [c5]Hiroaki Shikano, Machiko Asaie, Junji Yamamoto, Tatsuya Saito, Shunsuke Ota, Keitaro Uehara:
Study on supporting technology for operational procedure design of IT systems in cloud-era datacenters. SAC 2013: 405-407 - 2011
- [j5]Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
:
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. Trans. High Perform. Embed. Archit. Compil. 4: 215-233 (2011)
2000 – 2009
- 2008
- [j4]Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor. IEICE Trans. Electron. 91-C(4): 432-439 (2008) - [j3]Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara:
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array. IEICE Trans. Electron. 91-C(4): 553-561 (2008) - [j2]Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. IEEE J. Solid State Circuits 43(4): 902-910 (2008) - [c4]Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC 2008: 736-741 - 2007
- [c3]Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor. PACT 2007: 427 - 2005
- [c2]Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara:
Performance Evaluation of Compiler Controlled Power Saving Scheme. ISHPC 2005: 480-493 - [c1]Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara:
Compiler Control Power Saving Scheme for Multi Core Processors. LCPC 2005: 362-376 - 2003
- [j1]Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano:
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications. IEEE J. Solid State Circuits 38(7): 1220-1226 (2003)
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