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2020 – today
- 2023
[j1]Naofumi Hama, Masayoshi Mase, Art B. Owen:
Deletion and Insertion Tests in Regression Models. J. Mach. Learn. Res. 24: 290:1-290:38 (2023)- 2022
- [c13]Ryo Soga, Hideyuki Kanuka, Daisuke Fukui, Masayoshi Mase:
Risk assessment to design business process incorporating AI tasks. APSEC 2022: 582-583 - [i6]Naofumi Hama, Masayoshi Mase, Art B. Owen:
Deletion and Insertion Tests in Regression Models. CoRR abs/2205.12423 (2022) - [i5]Masayoshi Mase, Art B. Owen, Benjamin B. Seiler:
Variable importance without impossible data. CoRR abs/2205.15750 (2022) - [i4]Naofumi Hama, Masayoshi Mase, Art B. Owen:
Model free Shapley values for high dimensional data. CoRR abs/2211.08414 (2022) - 2021
- [i3]Masayoshi Mase, Art B. Owen, Benjamin B. Seiler:
Cohort Shapley value for algorithmic fairness. CoRR abs/2105.07168 (2021) - [i2]Benjamin Seiler, Masayoshi Mase, Art B. Owen:
What makes you unique? CoRR abs/2105.08013 (2021) - 2020
- [c12]Yuyao Wang, Masayoshi Mase, Masashi Egi:
Attribution-based Salience Method towards Interpretable Reinforcement Learning. AAAI Spring Symposium: Combining Machine Learning with Knowledge Engineering (1) 2020
2010 – 2019
- 2019
- [i1]Masayoshi Mase, Art B. Owen, Benjamin Seiler:
Explaining black box decisions by Shapley cohort refinement. CoRR abs/1911.00467 (2019) - 2017
- [c11]Hironori Kasahara
, Keiji Kimura, Boma A. Adhi, Yuhei Hosokawa, Yohei Kishimoto, Masayoshi Mase:
Multicore Cache Coherence Control by a Parallelizing Compiler. COMPSAC (1) 2017: 492-497 - [c10]Boma A. Adhi, Masayoshi Mase, Yuhei Hosokawa, Yohei Kishimoto, Taisuke Onishi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara:
Software Cache Coherent Control by Parallelizing Compiler. LCPC 2017: 17-25 - 2012
- [c9]Masayoshi Mase, Jun Okitsu, Eiichi Suzuki, Tohru Nojiri, Kentaro Sano, Hayato Shimizu:
Cooling efficiency aware workload placement using historical sensor data on IT-facility collaborative control. IGCC 2012: 1-6 - 2011
- [c8]Hiroki Mikami, Shumpei Kitaki, Masayoshi Mase, Akihiro Hayashi, Mamoru Shimaoka, Keiji Kimura, Masato Edahiro, Hironori Kasahara:
Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-Power Multicore. LCPC 2011: 31-45 - 2010
- [c7]Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara:
Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores. LCPC 2010: 184-198
2000 – 2009
- 2009
- [c6]Kosuke Kawazu, Masakazu Murao, Takeru Ohta, Masayoshi Mase, Takashi Maeno:
A System to Construct an Interest Model of User Based on Information in Browsed Web Page by User. HCI (3) 2009: 304-313 - [c5]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara:
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517 - [c4]Keiji Kimura, Masayoshi Mase, Hiroki Mikami, Takamichi Miyamoto, Jun Shirako, Hironori Kasahara:
OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers. LCPC 2009: 188-202 - 2008
- [c3]Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC 2008: 736-741 - [c2]Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara:
Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. ISPA 2008: 600-607 - [c1]Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91
Coauthor Index
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