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ORCID36th ISMVL 2006: Singapore
- 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore. IEEE Computer Society 2006, ISBN 0-7695-2532-6
Introduction
- Message from the Symposium Chairs.
- Message from the Program Chair.
- Organizing Committee.
- List of Reviewers.
Session 1: Invited Address
- Tsutomu Sasao:
Design Methods for Multiple-Valued Input Address Generators. 1
Session 2: Circuits I
- Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. 2 - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Designs of Radix Converters Using Arithmetic Decompositions. 3 - Eun-Ju Choi, Kyoung-Rok Cho, Je-Hoon Lee:
New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design. 4 - Akira Mochizuki, Takahiro Hanyu:
Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. 5 - Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama:
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. 6
Session 3: Algebra and Logic
- Sergiu Rudeanu, Dan A. Simovici:
On the Ranges of Algebraic Functions in Lattices - A Preliminary Report. 7 - Hisayuki Tatsumi, Masahiro Miyakawa, Masao Mukaidono:
Upper and Lower Bounds on the Number of Disjunctive Forms. 8 - Matthias Baaz
, Norbert Preining, Richard Zach:
Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta. 9 - Daniel Stamate:
Assumption based multi-valued semantics for extended logic programs. 10
Session 4: Circuits II
- Tsutomu Sasao, Jon T. Butler:
Implementation of Multiple-Valued CAM Functions by LUT Cascades. 11 - Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu:
The new architecture of radix-4 Chinese abacus adder. 12 - Haque Mohammad Munirul, Michitaka Kameyama:
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. 13 - Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. 14 - los Roberto Mingoto Jr.:
A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors. 15
Session 5: Invited Address
- Jaakko Astola, Radomir S. Stankovic:
Signal Processing Algorithms and Multiple-Valued Logic Design Methods. 16
Session 6: Circuits III
- Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama:
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. 17 - Henning Gundersen, Yngvar Berg:
A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices. 18 - Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. 19 - Mitsuhiro Tanihata, Takao Waho:
A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter. 20
Session 7: Algebra and Clones
- Jovanka Pantovic, Gradimir Vojvodic:
Commuting Hyperoperations. 21 - Lucien Haddad, Hajime Machida, Ivo G. Rosenberg:
Theoretical Basis of Commutation Theory for Partial Clones. 22 - Masahiro Miyakawa, Ivo G. Rosenberg, Hisayuki Tatsumi:
Associativity Test in Hypergroupoids. 23 - Hajime Machida, Michael Pinsker:
Some Observations on Minimal Clones. 24
Session 8: Systems and Satisfiability
- Görschwin Fey, Junhao Shi, Rolf Drechsler:
Efficiency of Multi-Valued Encoding in SAT-based ATPG. 25 - Josep Argelich, Xavier Domingo, Chu Min Li, Felip Manyà, Jordi Planes:
Towards Solving Many-Valued MaxSAT. 26 - Elena Dubrova:
Random Multiple-Valued Networks: Theory and Applications. 27
Session 9: Decision Diagrams and Decision Trees
- Tsutomu Sasao, Shinobu Nagayama:
Representations of Elementary Functions Using Binary Moment Diagrams. 28 - Svetlana N. Yanushkevich, Vlad P. Shmerko, Oleg Boulanov:
Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and Diagrams. 29 - D. Michael Miller, Mitchell A. Thornton:
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. 30 - Bogdan J. Falkowski, Shixing Yan:
Arithmetic-Haar Spectral Transform Decision Diagrams. 31
Session 10: Quantum Logic and Spectral Techniques
- Michael Katz:
Multi-Valued Quantum Logic. 32 - Lun Li, Mitchell A. Thornton, Marek A. Perkowski:
A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form. 33 - Bogdan J. Falkowski, Cheng Fu:
Generation and Relation of Quaternary and Binary Linearly Independent Transforms. 34 - Claudio Moraga, Radomir S. Stankovic, Jaakko Astola:
Properties of matrix-valued spectral coefficients obtained with the Fourier Transform on a non-Abelian group. 35
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