default search action
"Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching ..."
Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama (2005)
- Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama:
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 619-632 (2005)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.