"Clock skew estimate modeling for FPGA high-level synthesis and its ..."

Koichi Fujiwara et al. (2015)

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DOI: 10.1109/ASICON.2015.7516905

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
Clock skew estimate modeling for FPGA high-level synthesis and its application. ASICON 2015: 1-4

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