"A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core ..."

Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (2013)

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DOI: 10.1587/TRANSFUN.E96.A.1283

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type: Journal Article

metadata version: 2020-10-26

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Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1283-1292 (2013)

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